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9d6d6c67180533464fc839a8a6da182226cb3ee2
gem5/src/mem
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Nilay Vaish 9d6d6c6718 ruby: replace Time with Tick in replacement policy classes
2013-02-10 21:43:08 -06:00
..
cache
cache: remove drainManager because it's not used
2013-01-28 20:19:42 -05:00
config
mem: Remove the IIC replacement policy
2013-01-07 13:05:39 -05:00
protocol
ruby: replaces Time with Cycles in many places
2013-02-10 21:26:24 -06:00
ruby
ruby: replace Time with Tick in replacement policy classes
2013-02-10 21:43:08 -06:00
slicc
ruby: replace Time with Cycles in Message class
2013-02-10 21:26:24 -06:00
abstract_mem.cc
base: Encapsulate the underlying fields in AddrRange
2013-01-07 13:05:38 -05:00
abstract_mem.hh
base: Encapsulate the underlying fields in AddrRange
2013-01-07 13:05:38 -05:00
AbstractMemory.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
addr_mapper.cc
mem: Skip address mapper range checks to allow more flexibility
2013-01-07 13:05:38 -05:00
addr_mapper.hh
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
AddrMapper.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
bridge.cc
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
bridge.hh
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
Bridge.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
bus.cc
mem: Tidy up bus addr range debug messages
2013-01-07 13:05:38 -05:00
bus.hh
base: Encapsulate the underlying fields in AddrRange
2013-01-07 13:05:38 -05:00
Bus.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
coherent_bus.cc
sim: Move the draining interface into a separate base class
2012-11-02 11:32:01 -05:00
coherent_bus.hh
sim: Move the draining interface into a separate base class
2012-11-02 11:32:01 -05:00
comm_monitor.cc
mem: Add tracing support in the communication monitor
2013-01-07 13:05:37 -05:00
comm_monitor.hh
mem: Add tracing support in the communication monitor
2013-01-07 13:05:37 -05:00
CommMonitor.py
mem: Add tracing support in the communication monitor
2013-01-07 13:05:37 -05:00
fs_translating_port_proxy.cc
mem: fix bug with CopyStringOut and null string termination.
2012-05-10 18:04:27 -05:00
fs_translating_port_proxy.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
mem_object.cc
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
mem_object.hh
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
MemObject.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
mport.cc
MEM: Separate snoops and normal memory requests/responses
2012-04-14 05:45:07 -04:00
mport.hh
MEM: Separate requests and responses for timing accesses
2012-05-01 13:40:42 -04:00
noncoherent_bus.cc
sim: Move the draining interface into a separate base class
2012-11-02 11:32:01 -05:00
noncoherent_bus.hh
sim: Move the draining interface into a separate base class
2012-11-02 11:32:01 -05:00
packet_access.hh
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
2009-09-23 08:34:21 -07:00
packet_queue.cc
mem: Add sanity check to packet queue size
2013-01-07 13:05:35 -05:00
packet_queue.hh
sim: have a curTick per eventq
2012-11-16 10:27:47 -06:00
packet.cc
Packet: Remove NACKs from packet and its use in endpoints
2012-08-22 11:39:59 -04:00
packet.hh
mem: Add a gasket that allows memory ranges to be re-mapped.
2012-09-25 11:49:40 -05:00
page_table.cc
Fix: Address a few benign memory leaks
2012-07-09 12:35:30 -04:00
page_table.hh
SE/FS: Get rid of includes of config/full_system.hh.
2011-11-18 02:20:22 -08:00
physical.cc
mem: Merge ranges that are part of the conf table
2013-01-07 13:05:38 -05:00
physical.hh
mem: Merge ranges that are part of the conf table
2013-01-07 13:05:38 -05:00
port_proxy.cc
MEM: Remove the Broadcast destination from the packet
2012-04-14 05:45:55 -04:00
port_proxy.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
port.cc
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
port.hh
mem: Fix typo in port comments
2012-10-31 09:28:23 -04:00
qport.hh
sim: Move the draining interface into a separate base class
2012-11-02 11:32:01 -05:00
request.hh
ARM: dump stats and process info on context switches
2012-11-02 11:32:01 -05:00
SConscript
mem: Add tracing support in the communication monitor
2013-01-07 13:05:37 -05:00
se_translating_port_proxy.cc
SETranslatingPortProxy: fix bug in tryReadString()
2012-08-06 16:57:11 -07:00
se_translating_port_proxy.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
simple_dram.cc
mem: Add comments for the DRAM address decoding
2013-01-31 07:49:18 -05:00
simple_dram.hh
mem: Add tTAW and tFAW to the SimpleDRAM model
2013-01-31 07:49:14 -05:00
simple_mem.cc
mem: Fix use-after-free bug
2013-01-08 08:54:06 -05:00
simple_mem.hh
mem: fix use after free issue in memories until 4-phase work complete.
2012-11-02 11:50:16 -05:00
SimpleDRAM.py
mem: Add DDR3 and LPDDR2 DRAM controller configurations
2013-01-31 07:49:14 -05:00
SimpleMemory.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
tport.cc
Port: Extend the QueuedPort interface and use where appropriate
2012-08-22 11:39:56 -04:00
tport.hh
Port: Hide the queue implementation in SimpleTimingPort
2012-07-09 12:35:42 -04:00