Ayaz Akram 14663f9c48 arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use ...

This change adds assembly code for riscv pseudo instructions so
that they can be used with riscv benchmarks.

Change-Id: Ic979fd375e7750e92f52b900bf39e351f629fe2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38515
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-01-20 09:40:09 +00:00

..

arm

util: Teach the m5 utility's scons how to run unit tests.

2020-12-04 01:39:34 +00:00

arm64

util: Rename the aarch64 m5 util version to arm64.

2020-12-04 11:13:50 +00:00

riscv

arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use

2021-01-20 09:40:09 +00:00

sparc

util: Teach the m5 utility's scons how to run unit tests.

2020-12-04 01:39:34 +00:00

thumb

util: Teach the m5 utility's scons how to run unit tests.

2020-12-04 01:39:34 +00:00

x86

util: Teach the m5 utility's scons how to run unit tests.

2020-12-04 01:39:34 +00:00