43a1ea88b8
This is the rest of the code for part 2. See http://learning.gem5.org/book/part2/simplecache.html Change-Id: I5db099266a1196914656be3858fdd5fb4f8eab48 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5023 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
467 lines
14 KiB
C++
467 lines
14 KiB
C++
/*
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* Copyright (c) 2017 Jason Lowe-Power
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Jason Lowe-Power
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*/
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#include "learning_gem5/part2/simple_cache.hh"
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#include "base/random.hh"
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#include "debug/SimpleCache.hh"
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#include "sim/system.hh"
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SimpleCache::SimpleCache(SimpleCacheParams *params) :
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MemObject(params),
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latency(params->latency),
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blockSize(params->system->cacheLineSize()),
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capacity(params->size / blockSize),
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memPort(params->name + ".mem_side", this),
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blocked(false), originalPacket(nullptr), waitingPortId(-1)
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{
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// Since the CPU side ports are a vector of ports, create an instance of
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// the CPUSidePort for each connection. This member of params is
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// automatically created depending on the name of the vector port and
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// holds the number of connections to this port name
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for (int i = 0; i < params->port_cpu_side_connection_count; ++i) {
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cpuPorts.emplace_back(name() + csprintf(".cpu_side[%d]", i), i, this);
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}
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}
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BaseMasterPort&
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SimpleCache::getMasterPort(const std::string& if_name, PortID idx)
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{
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panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
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// This is the name from the Python SimObject declaration in SimpleCache.py
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if (if_name == "mem_side") {
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return memPort;
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} else {
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// pass it along to our super class
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return MemObject::getMasterPort(if_name, idx);
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}
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}
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BaseSlavePort&
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SimpleCache::getSlavePort(const std::string& if_name, PortID idx)
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{
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// This is the name from the Python SimObject declaration (SimpleMemobj.py)
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if (if_name == "cpu_side" && idx < cpuPorts.size()) {
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// We should have already created all of the ports in the constructor
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return cpuPorts[idx];
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} else {
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// pass it along to our super class
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return MemObject::getSlavePort(if_name, idx);
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}
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}
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void
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SimpleCache::CPUSidePort::sendPacket(PacketPtr pkt)
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{
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// Note: This flow control is very simple since the cache is blocking.
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panic_if(blockedPacket != nullptr, "Should never try to send if blocked!");
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// If we can't send the packet across the port, store it for later.
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DPRINTF(SimpleCache, "Sending %s to CPU\n", pkt->print());
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if (!sendTimingResp(pkt)) {
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DPRINTF(SimpleCache, "failed!\n");
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blockedPacket = pkt;
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}
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}
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AddrRangeList
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SimpleCache::CPUSidePort::getAddrRanges() const
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{
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return owner->getAddrRanges();
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}
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void
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SimpleCache::CPUSidePort::trySendRetry()
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{
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if (needRetry && blockedPacket == nullptr) {
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// Only send a retry if the port is now completely free
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needRetry = false;
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DPRINTF(SimpleCache, "Sending retry req.\n");
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sendRetryReq();
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}
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}
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void
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SimpleCache::CPUSidePort::recvFunctional(PacketPtr pkt)
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{
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// Just forward to the cache.
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return owner->handleFunctional(pkt);
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}
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bool
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SimpleCache::CPUSidePort::recvTimingReq(PacketPtr pkt)
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{
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DPRINTF(SimpleCache, "Got request %s\n", pkt->print());
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if (blockedPacket || needRetry) {
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// The cache may not be able to send a reply if this is blocked
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DPRINTF(SimpleCache, "Request blocked\n");
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needRetry = true;
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return false;
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}
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// Just forward to the cache.
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if (!owner->handleRequest(pkt, id)) {
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DPRINTF(SimpleCache, "Request failed\n");
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// stalling
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needRetry = true;
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return false;
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} else {
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DPRINTF(SimpleCache, "Request succeeded\n");
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return true;
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}
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}
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void
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SimpleCache::CPUSidePort::recvRespRetry()
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{
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// We should have a blocked packet if this function is called.
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assert(blockedPacket != nullptr);
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// Grab the blocked packet.
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PacketPtr pkt = blockedPacket;
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blockedPacket = nullptr;
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DPRINTF(SimpleCache, "Retrying response pkt %s\n", pkt->print());
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// Try to resend it. It's possible that it fails again.
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sendPacket(pkt);
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// We may now be able to accept new packets
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trySendRetry();
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}
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void
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SimpleCache::MemSidePort::sendPacket(PacketPtr pkt)
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{
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// Note: This flow control is very simple since the cache is blocking.
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panic_if(blockedPacket != nullptr, "Should never try to send if blocked!");
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// If we can't send the packet across the port, store it for later.
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if (!sendTimingReq(pkt)) {
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blockedPacket = pkt;
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}
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}
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bool
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SimpleCache::MemSidePort::recvTimingResp(PacketPtr pkt)
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{
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// Just forward to the cache.
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return owner->handleResponse(pkt);
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}
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void
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SimpleCache::MemSidePort::recvReqRetry()
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{
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// We should have a blocked packet if this function is called.
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assert(blockedPacket != nullptr);
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// Grab the blocked packet.
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PacketPtr pkt = blockedPacket;
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blockedPacket = nullptr;
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// Try to resend it. It's possible that it fails again.
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sendPacket(pkt);
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}
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void
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SimpleCache::MemSidePort::recvRangeChange()
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{
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owner->sendRangeChange();
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}
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bool
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SimpleCache::handleRequest(PacketPtr pkt, int port_id)
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{
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if (blocked) {
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// There is currently an outstanding request so we can't respond. Stall
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return false;
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}
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DPRINTF(SimpleCache, "Got request for addr %#x\n", pkt->getAddr());
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// This cache is now blocked waiting for the response to this packet.
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blocked = true;
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// Store the port for when we get the response
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assert(waitingPortId == -1);
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waitingPortId = port_id;
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// Schedule an event after cache access latency to actually access
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schedule(new EventFunctionWrapper([this, pkt]{ accessTiming(pkt); },
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name() + ".accessEvent", true),
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clockEdge(latency));
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return true;
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}
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bool
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SimpleCache::handleResponse(PacketPtr pkt)
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{
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assert(blocked);
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DPRINTF(SimpleCache, "Got response for addr %#x\n", pkt->getAddr());
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// For now assume that inserts are off of the critical path and don't count
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// for any added latency.
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insert(pkt);
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missLatency.sample(curTick() - missTime);
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// If we had to upgrade the request packet to a full cache line, now we
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// can use that packet to construct the response.
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if (originalPacket != nullptr) {
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DPRINTF(SimpleCache, "Copying data from new packet to old\n");
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// We had to upgrade a previous packet. We can functionally deal with
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// the cache access now. It better be a hit.
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bool hit M5_VAR_USED = accessFunctional(originalPacket);
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panic_if(!hit, "Should always hit after inserting");
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originalPacket->makeResponse();
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delete pkt; // We may need to delay this, I'm not sure.
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pkt = originalPacket;
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originalPacket = nullptr;
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} // else, pkt contains the data it needs
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sendResponse(pkt);
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return true;
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}
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void SimpleCache::sendResponse(PacketPtr pkt)
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{
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assert(blocked);
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DPRINTF(SimpleCache, "Sending resp for addr %#x\n", pkt->getAddr());
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int port = waitingPortId;
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// The packet is now done. We're about to put it in the port, no need for
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// this object to continue to stall.
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// We need to free the resource before sending the packet in case the CPU
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// tries to send another request immediately (e.g., in the same callchain).
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blocked = false;
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waitingPortId = -1;
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// Simply forward to the memory port
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cpuPorts[port].sendPacket(pkt);
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// For each of the cpu ports, if it needs to send a retry, it should do it
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// now since this memory object may be unblocked now.
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for (auto& port : cpuPorts) {
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port.trySendRetry();
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}
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}
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void
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SimpleCache::handleFunctional(PacketPtr pkt)
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{
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if (accessFunctional(pkt)) {
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pkt->makeResponse();
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} else {
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memPort.sendFunctional(pkt);
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}
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}
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void
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SimpleCache::accessTiming(PacketPtr pkt)
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{
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bool hit = accessFunctional(pkt);
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DPRINTF(SimpleCache, "%s for packet: %s\n", hit ? "Hit" : "Miss",
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pkt->print());
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if (hit) {
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// Respond to the CPU side
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hits++; // update stats
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DDUMP(SimpleCache, pkt->getConstPtr<uint8_t>(), pkt->getSize());
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pkt->makeResponse();
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sendResponse(pkt);
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} else {
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misses++; // update stats
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missTime = curTick();
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// Forward to the memory side.
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// We can't directly forward the packet unless it is exactly the size
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// of the cache line, and aligned. Check for that here.
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Addr addr = pkt->getAddr();
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Addr block_addr = pkt->getBlockAddr(blockSize);
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unsigned size = pkt->getSize();
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if (addr == block_addr && size == blockSize) {
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// Aligned and block size. We can just forward.
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DPRINTF(SimpleCache, "forwarding packet\n");
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memPort.sendPacket(pkt);
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} else {
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DPRINTF(SimpleCache, "Upgrading packet to block size\n");
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panic_if(addr - block_addr + size > blockSize,
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"Cannot handle accesses that span multiple cache lines");
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// Unaligned access to one cache block
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assert(pkt->needsResponse());
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MemCmd cmd;
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if (pkt->isWrite() || pkt->isRead()) {
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// Read the data from memory to write into the block.
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// We'll write the data in the cache (i.e., a writeback cache)
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cmd = MemCmd::ReadReq;
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} else {
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panic("Unknown packet type in upgrade size");
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}
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// Create a new packet that is blockSize
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PacketPtr new_pkt = new Packet(pkt->req, cmd, blockSize);
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new_pkt->allocate();
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// Should now be block aligned
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assert(new_pkt->getAddr() == new_pkt->getBlockAddr(blockSize));
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// Save the old packet
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originalPacket = pkt;
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DPRINTF(SimpleCache, "forwarding packet\n");
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memPort.sendPacket(new_pkt);
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}
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}
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}
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bool
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SimpleCache::accessFunctional(PacketPtr pkt)
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{
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Addr block_addr = pkt->getBlockAddr(blockSize);
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auto it = cacheStore.find(block_addr);
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if (it != cacheStore.end()) {
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if (pkt->isWrite()) {
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// Write the data into the block in the cache
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pkt->writeDataToBlock(it->second, blockSize);
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} else if (pkt->isRead()) {
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// Read the data out of the cache block into the packet
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pkt->setDataFromBlock(it->second, blockSize);
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} else {
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panic("Unknown packet type!");
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}
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return true;
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}
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return false;
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}
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void
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SimpleCache::insert(PacketPtr pkt)
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{
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// The packet should be aligned.
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assert(pkt->getAddr() == pkt->getBlockAddr(blockSize));
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// The address should not be in the cache
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assert(cacheStore.find(pkt->getAddr()) == cacheStore.end());
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// The pkt should be a response
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assert(pkt->isResponse());
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if (cacheStore.size() >= capacity) {
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// Select random thing to evict. This is a little convoluted since we
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// are using a std::unordered_map. See http://bit.ly/2hrnLP2
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int bucket, bucket_size;
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do {
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bucket = random_mt.random(0, (int)cacheStore.bucket_count() - 1);
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} while ( (bucket_size = cacheStore.bucket_size(bucket)) == 0 );
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auto block = std::next(cacheStore.begin(bucket),
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random_mt.random(0, bucket_size - 1));
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DPRINTF(SimpleCache, "Removing addr %#x\n", block->first);
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// Write back the data.
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// Create a new request-packet pair
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RequestPtr req = new Request(block->first, blockSize, 0, 0);
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PacketPtr new_pkt = new Packet(req, MemCmd::WritebackDirty, blockSize);
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new_pkt->dataDynamic(block->second); // This will be deleted later
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DPRINTF(SimpleCache, "Writing packet back %s\n", pkt->print());
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// Send the write to memory
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memPort.sendPacket(new_pkt);
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// Delete this entry
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cacheStore.erase(block->first);
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}
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DPRINTF(SimpleCache, "Inserting %s\n", pkt->print());
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DDUMP(SimpleCache, pkt->getConstPtr<uint8_t>(), blockSize);
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// Allocate space for the cache block data
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uint8_t *data = new uint8_t[blockSize];
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// Insert the data and address into the cache store
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cacheStore[pkt->getAddr()] = data;
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// Write the data into the cache
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pkt->writeDataToBlock(data, blockSize);
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}
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AddrRangeList
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SimpleCache::getAddrRanges() const
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{
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DPRINTF(SimpleCache, "Sending new ranges\n");
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// Just use the same ranges as whatever is on the memory side.
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return memPort.getAddrRanges();
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}
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void
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SimpleCache::sendRangeChange() const
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{
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for (auto& port : cpuPorts) {
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port.sendRangeChange();
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}
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}
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void
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SimpleCache::regStats()
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{
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// If you don't do this you get errors about uninitialized stats.
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MemObject::regStats();
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hits.name(name() + ".hits")
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.desc("Number of hits")
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;
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misses.name(name() + ".misses")
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.desc("Number of misses")
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;
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missLatency.name(name() + ".missLatency")
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.desc("Ticks for misses to the cache")
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.init(16) // number of buckets
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;
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hitRatio.name(name() + ".hitRatio")
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.desc("The ratio of hits to the total accesses to the cache")
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;
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hitRatio = hits / (hits + misses);
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}
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SimpleCache*
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SimpleCacheParams::create()
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{
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return new SimpleCache(this);
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}
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