42b56ceb7b
The memory manager is responsible for reading and writes to VRAM memory for direct requests that bypass GPU caches. Change-Id: I4aa1e77737ce52f2f2c01929b58984126bdcb925 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51850 Maintainer: Matt Sinclair <mattdsinclair@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
119 lines
4.0 KiB
C++
119 lines
4.0 KiB
C++
/*
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* Copyright (c) 2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include "dev/amdgpu/memory_manager.hh"
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#include <memory>
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#include "base/chunk_generator.hh"
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#include "debug/AMDGPUMem.hh"
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#include "params/AMDGPUMemoryManager.hh"
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#include "sim/system.hh"
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namespace gem5
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{
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AMDGPUMemoryManager::AMDGPUMemoryManager(const AMDGPUMemoryManagerParams &p)
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: ClockedObject(p), _gpuMemPort(csprintf("%s-port", name()), this),
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cacheLineSize(p.system->cacheLineSize()),
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_requestorId(p.system->getRequestorId(this))
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{
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}
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void
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AMDGPUMemoryManager::writeRequest(Addr addr, uint8_t *data, int size,
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Request::Flags flag, Event *callback)
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{
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assert(data);
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ChunkGenerator gen(addr, size, cacheLineSize);
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for (; !gen.done(); gen.next()) {
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RequestPtr req = std::make_shared<Request>(gen.addr(), gen.size(),
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flag, _requestorId);
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PacketPtr pkt = Packet::createWrite(req);
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uint8_t *dataPtr = new uint8_t[gen.size()];
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std::memcpy(dataPtr, data + (gen.complete()/sizeof(uint8_t)),
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gen.size());
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pkt->dataDynamic<uint8_t>(dataPtr);
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// We only want to issue the callback on the last request completing.
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if (gen.last()) {
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pkt->pushSenderState(new GPUMemPort::SenderState(callback, addr));
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} else {
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pkt->pushSenderState(new GPUMemPort::SenderState(nullptr, addr));
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}
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if (!_gpuMemPort.sendTimingReq(pkt)) {
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DPRINTF(AMDGPUMem, "Request to %#lx needs retry\n", gen.addr());
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_gpuMemPort.retries.push_back(pkt);
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} else {
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DPRINTF(AMDGPUMem, "Write request to %#lx sent\n", gen.addr());
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}
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}
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}
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bool
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AMDGPUMemoryManager::GPUMemPort::recvTimingResp(PacketPtr pkt)
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{
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// Retrieve sender state
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[[maybe_unused]] SenderState *sender_state =
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safe_cast<SenderState*>(pkt->senderState);
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DPRINTF(AMDGPUMem, "Recveived Response for %#x\n", sender_state->_addr);
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// Check if there is a callback event and if so call it
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if (sender_state->_callback) {
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sender_state->_callback->process();
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delete sender_state->_callback;
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}
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delete pkt->senderState;
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delete pkt;
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return true;
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}
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void
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AMDGPUMemoryManager::GPUMemPort::recvReqRetry()
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{
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for (const auto &pkt : retries) {
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if (!sendTimingReq(pkt)) {
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break;
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} else {
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DPRINTF(AMDGPUMem, "Retry for %#lx sent\n", pkt->getAddr());
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retries.pop_front();
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}
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}
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}
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} // namespace gem5
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