derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175
gem5/src/cpu/o3
History
Mrinmoy Ghosh 9b05e96b9e BPred: Fix RAS to handle predicated call/return instructions. 
Change RAS to fix issues with predicated call/return instructions.
Handled all cases in the life of a predicated call and return instruction.
2012-02-13 12:26:25 -06:00
..
base_dyn_inst.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
bpred_unit_impl.hh
BPred: Fix RAS to handle predicated call/return instructions.
2012-02-13 12:26:25 -06:00
bpred_unit.cc
now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
2006-06-30 20:49:31 -04:00
bpred_unit.hh
BPred: Fix RAS to handle predicated call/return instructions.
2012-02-13 12:26:25 -06:00
checker_builder.cc
Merge with head, hopefully the last time for this batch.
2012-01-31 22:40:08 -08:00
comm.hh
O3: When squashing, restore the macroop that should be used for fetching.
2011-08-14 17:41:34 -07:00
commit_impl.hh
BPred: Fix RAS to handle predicated call/return instructions.
2012-02-13 12:26:25 -06:00
commit.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
commit.hh
cpu: add separate stats for insts/ops both globally and per cpu model
2012-02-12 16:07:39 -06:00
cpu_builder.cc
SE/FS: Get rid of includes of config/full_system.hh.
2011-11-18 02:20:22 -08:00
cpu_policy.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
cpu.cc
cpu: add separate stats for insts/ops both globally and per cpu model
2012-02-12 16:07:39 -06:00
cpu.hh
cpu: add separate stats for insts/ops both globally and per cpu model
2012-02-12 16:07:39 -06:00
decode_impl.hh
BP: Fix several Branch Predictor issues.
2012-02-13 12:26:24 -06:00
decode.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
decode.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
dep_graph.hh
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
2010-10-31 00:07:20 -07:00
dyn_inst_impl.hh
Merge with head, hopefully the last time for this batch.
2012-01-31 22:40:08 -08:00
dyn_inst.cc
O3: Generaize the O3 IMPL class so it isn't split out by ISA.
2008-10-09 00:10:02 -07:00
dyn_inst.hh
SE/FS: Expose the same methods on the CPUs in SE and FS modes.
2011-11-01 04:01:13 -07:00
fetch_impl.hh
mem: Add a master ID to each request object.
2012-02-12 16:07:38 -06:00
fetch.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
fetch.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
free_list.cc
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
free_list.hh
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
fu_pool.cc
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
fu_pool.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
FuncUnitConfig.py
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
2010-11-15 14:04:04 -06:00
FUPool.py
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
2010-11-15 14:04:04 -06:00
iew_impl.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
iew.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
iew.hh
Merge with head, hopefully the last time for this batch.
2012-01-31 22:40:08 -08:00
impl.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
inst_queue_impl.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
inst_queue.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
inst_queue.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
isa_specific.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
lsq_impl.hh
CPU: Moving towards a more general port across CPU models
2012-01-17 12:55:08 -06:00
lsq_unit_impl.hh
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
2012-01-31 07:46:03 -08:00
lsq_unit.cc
now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
2006-06-30 20:49:31 -04:00
lsq_unit.hh
Faults: Turn off arch/faults.hh
2012-02-07 04:43:21 -08:00
lsq.cc
now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
2006-06-30 20:49:31 -04:00
lsq.hh
Merge with head, hopefully the last time for this batch.
2012-01-31 22:40:08 -08:00
mem_dep_unit_impl.hh
LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
2011-08-19 15:08:07 -05:00
mem_dep_unit.cc
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
mem_dep_unit.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
O3Checker.py
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
2012-01-31 07:46:03 -08:00
O3CPU.py
Merge with head, hopefully the last time for this batch.
2012-01-31 22:40:08 -08:00
regfile.hh
SE/FS: Get rid of includes of config/full_system.hh.
2011-11-18 02:20:22 -08:00
rename_impl.hh
Merge yet again with the main repository.
2012-01-16 04:27:10 -08:00
rename_map.cc
o3: missing newlines on some dprintfs
2011-06-10 22:15:32 -04:00
rename_map.hh
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
2009-09-23 08:34:21 -07:00
rename.cc
now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
2006-06-30 20:49:31 -04:00
rename.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
rob_impl.hh
O3 CPU: Provide the squashing instruction
2012-02-10 08:37:28 -06:00
rob.cc
now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
2006-06-30 20:49:31 -04:00
rob.hh
O3 CPU: Provide the squashing instruction
2012-02-10 08:37:28 -06:00
sat_counter.cc
Merge ktlim@zizzer:/bk/newmem
2006-06-02 18:19:50 -04:00
sat_counter.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
SConscript
scons: rename TraceFlags to DebugFlags
2011-06-02 17:36:21 -07:00
SConsopts
cpu_models: get rid of cpu_models.py and move the stuff into SCons
2010-02-26 18:14:48 -08:00
scoreboard.cc
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
scoreboard.hh
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
store_set.cc
LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
2011-08-19 15:08:07 -05:00
store_set.hh
LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
2011-08-19 15:08:07 -05:00
thread_context_impl.hh
Merge with head, hopefully the last time for this batch.
2012-01-31 22:40:08 -08:00
thread_context.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
thread_context.hh
Merge with head, hopefully the last time for this batch.
2012-01-31 22:40:08 -08:00
thread_state.hh
Implement Ali's review feedback.
2012-01-29 02:04:34 -08:00