c58cb8c9db
This changeset adds support for partial (or masked) loads/stores, i.e. loads/stores that can disable accesses to individual bytes within the target address range. In addition, this changeset extends the code to crack memory accesses across most CPU models (TimingSimpleCPU still TBD), so that arbitrarily wide memory accesses are supported. These changes are required for supporting ISAs with wide vectors. Additional authors: - Gabor Dozsa <gabor.dozsa@arm.com> - Tiago Muck <tiago.muck@arm.com> Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13518 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
1025 lines
31 KiB
C++
1025 lines
31 KiB
C++
/*
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* Copyright (c) 2012-2013,2017-2018 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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* Steve Reinhardt
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* Ali Saidi
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*/
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/**
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* @file
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* Declaration of a request, the overall memory request consisting of
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the parts of the request that are persistent throughout the transaction.
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*/
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#ifndef __MEM_REQUEST_HH__
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#define __MEM_REQUEST_HH__
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#include <cassert>
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#include <climits>
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#include "base/flags.hh"
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#include "base/logging.hh"
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#include "base/types.hh"
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#include "cpu/inst_seq.hh"
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#include "sim/core.hh"
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/**
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* Special TaskIds that are used for per-context-switch stats dumps
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* and Cache Occupancy. Having too many tasks seems to be a problem
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* with vector stats. 1024 seems to be a reasonable number that
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* doesn't cause a problem with stats and is large enough to realistic
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* benchmarks (Linux/Android boot, BBench, etc.)
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*/
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namespace ContextSwitchTaskId {
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enum TaskId {
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MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
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Prefetcher = 1022, /* For cache lines brought in by prefetcher */
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DMA = 1023, /* Mostly Table Walker */
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Unknown = 1024,
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NumTaskId
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};
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}
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class Request;
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typedef std::shared_ptr<Request> RequestPtr;
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typedef uint16_t MasterID;
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class Request
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{
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public:
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typedef uint64_t FlagsType;
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typedef uint8_t ArchFlagsType;
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typedef ::Flags<FlagsType> Flags;
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enum : FlagsType {
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/**
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* Architecture specific flags.
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*
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* These bits int the flag field are reserved for
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* architecture-specific code. For example, SPARC uses them to
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* represent ASIs.
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*/
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ARCH_BITS = 0x000000FF,
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/** The request was an instruction fetch. */
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INST_FETCH = 0x00000100,
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/** The virtual address is also the physical address. */
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PHYSICAL = 0x00000200,
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/**
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* The request is to an uncacheable address.
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*
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* @note Uncacheable accesses may be reordered by CPU models. The
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* STRICT_ORDER flag should be set if such reordering is
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* undesirable.
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*/
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UNCACHEABLE = 0x00000400,
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/**
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* The request is required to be strictly ordered by <i>CPU
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* models</i> and is non-speculative.
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*
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* A strictly ordered request is guaranteed to never be
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* re-ordered or executed speculatively by a CPU model. The
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* memory system may still reorder requests in caches unless
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* the UNCACHEABLE flag is set as well.
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*/
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STRICT_ORDER = 0x00000800,
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/** This request is to a memory mapped register. */
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MMAPPED_IPR = 0x00002000,
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/** This request is made in privileged mode. */
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PRIVILEGED = 0x00008000,
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/**
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* This is a write that is targeted and zeroing an entire
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* cache block. There is no need for a read/modify/write
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*/
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CACHE_BLOCK_ZERO = 0x00010000,
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/** The request should not cause a memory access. */
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NO_ACCESS = 0x00080000,
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/**
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* This request will lock or unlock the accessed memory. When
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* used with a load, the access locks the particular chunk of
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* memory. When used with a store, it unlocks. The rule is
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* that locked accesses have to be made up of a locked load,
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* some operation on the data, and then a locked store.
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*/
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LOCKED_RMW = 0x00100000,
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/** The request is a Load locked/store conditional. */
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LLSC = 0x00200000,
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/** This request is for a memory swap. */
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MEM_SWAP = 0x00400000,
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MEM_SWAP_COND = 0x00800000,
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/** The request is a prefetch. */
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PREFETCH = 0x01000000,
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/** The request should be prefetched into the exclusive state. */
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PF_EXCLUSIVE = 0x02000000,
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/** The request should be marked as LRU. */
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EVICT_NEXT = 0x04000000,
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/** The request should be marked with ACQUIRE. */
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ACQUIRE = 0x00020000,
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/** The request should be marked with RELEASE. */
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RELEASE = 0x00040000,
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/** The request is an atomic that returns data. */
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ATOMIC_RETURN_OP = 0x40000000,
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/** The request is an atomic that does not return data. */
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ATOMIC_NO_RETURN_OP = 0x80000000,
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/** The request should be marked with KERNEL.
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* Used to indicate the synchronization associated with a GPU kernel
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* launch or completion.
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*/
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KERNEL = 0x00001000,
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/**
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* The request should be handled by the generic IPR code (only
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* valid together with MMAPPED_IPR)
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*/
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GENERIC_IPR = 0x08000000,
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/** The request targets the secure memory space. */
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SECURE = 0x10000000,
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/** The request is a page table walk */
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PT_WALK = 0x20000000,
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/** The request invalidates a memory location */
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INVALIDATE = 0x0000000100000000,
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/** The request cleans a memory location */
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CLEAN = 0x0000000200000000,
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/** The request targets the point of unification */
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DST_POU = 0x0000001000000000,
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/** The request targets the point of coherence */
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DST_POC = 0x0000002000000000,
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/** Bits to define the destination of a request */
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DST_BITS = 0x0000003000000000,
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/**
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* These flags are *not* cleared when a Request object is
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* reused (assigned a new address).
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*/
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STICKY_FLAGS = INST_FETCH
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};
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static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO |
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CLEAN | INVALIDATE;
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/** Master Ids that are statically allocated
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* @{*/
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enum : MasterID {
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/** This master id is used for writeback requests by the caches */
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wbMasterId = 0,
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/**
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* This master id is used for functional requests that
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* don't come from a particular device
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*/
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funcMasterId = 1,
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/** This master id is used for message signaled interrupts */
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intMasterId = 2,
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/**
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* Invalid master id for assertion checking only. It is
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* invalid behavior to ever send this id as part of a request.
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*/
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invldMasterId = std::numeric_limits<MasterID>::max()
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};
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/** @} */
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typedef uint32_t MemSpaceConfigFlagsType;
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typedef ::Flags<MemSpaceConfigFlagsType> MemSpaceConfigFlags;
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enum : MemSpaceConfigFlagsType {
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/** Has a synchronization scope been set? */
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SCOPE_VALID = 0x00000001,
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/** Access has Wavefront scope visibility */
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WAVEFRONT_SCOPE = 0x00000002,
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/** Access has Workgroup scope visibility */
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WORKGROUP_SCOPE = 0x00000004,
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/** Access has Device (e.g., GPU) scope visibility */
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DEVICE_SCOPE = 0x00000008,
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/** Access has System (e.g., CPU + GPU) scope visibility */
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SYSTEM_SCOPE = 0x00000010,
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/** Global Segment */
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GLOBAL_SEGMENT = 0x00000020,
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/** Group Segment */
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GROUP_SEGMENT = 0x00000040,
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/** Private Segment */
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PRIVATE_SEGMENT = 0x00000080,
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/** Kergarg Segment */
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KERNARG_SEGMENT = 0x00000100,
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/** Readonly Segment */
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READONLY_SEGMENT = 0x00000200,
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/** Spill Segment */
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SPILL_SEGMENT = 0x00000400,
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/** Arg Segment */
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ARG_SEGMENT = 0x00000800,
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};
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private:
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typedef uint16_t PrivateFlagsType;
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typedef ::Flags<PrivateFlagsType> PrivateFlags;
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enum : PrivateFlagsType {
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/** Whether or not the size is valid. */
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VALID_SIZE = 0x00000001,
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/** Whether or not paddr is valid (has been written yet). */
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VALID_PADDR = 0x00000002,
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/** Whether or not the vaddr & asid are valid. */
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VALID_VADDR = 0x00000004,
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/** Whether or not the instruction sequence number is valid. */
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VALID_INST_SEQ_NUM = 0x00000008,
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/** Whether or not the pc is valid. */
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VALID_PC = 0x00000010,
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/** Whether or not the context ID is valid. */
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VALID_CONTEXT_ID = 0x00000020,
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/** Whether or not the sc result is valid. */
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VALID_EXTRA_DATA = 0x00000080,
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/** Whether or not the stream ID and substream ID is valid. */
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VALID_STREAM_ID = 0x00000100,
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VALID_SUBSTREAM_ID = 0x00000200,
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/**
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* These flags are *not* cleared when a Request object is reused
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* (assigned a new address).
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*/
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STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
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};
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private:
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/**
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* Set up a physical (e.g. device) request in a previously
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* allocated Request object.
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*/
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void
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setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
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{
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_paddr = paddr;
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_size = size;
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_time = time;
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_masterId = mid;
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_flags.clear(~STICKY_FLAGS);
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_flags.set(flags);
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privateFlags.clear(~STICKY_PRIVATE_FLAGS);
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privateFlags.set(VALID_PADDR|VALID_SIZE);
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depth = 0;
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accessDelta = 0;
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//translateDelta = 0;
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}
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/**
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* The physical address of the request. Valid only if validPaddr
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* is set.
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*/
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Addr _paddr;
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/**
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* The size of the request. This field must be set when vaddr or
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* paddr is written via setVirt() or setPhys(), so it is always
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* valid as long as one of the address fields is valid.
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*/
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unsigned _size;
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/** Byte-enable mask for writes. */
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std::vector<bool> _byteEnable;
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/** The requestor ID which is unique in the system for all ports
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* that are capable of issuing a transaction
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*/
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MasterID _masterId;
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/** Flag structure for the request. */
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Flags _flags;
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/** Memory space configuraiton flag structure for the request. */
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MemSpaceConfigFlags _memSpaceConfigFlags;
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/** Private flags for field validity checking. */
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PrivateFlags privateFlags;
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/**
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* The time this request was started. Used to calculate
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* latencies. This field is set to curTick() any time paddr or vaddr
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* is written.
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*/
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Tick _time;
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/**
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* The task id associated with this request
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*/
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uint32_t _taskId;
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union {
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struct {
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/**
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* The stream ID uniquely identifies a device behind the
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* SMMU/IOMMU Each transaction arriving at the SMMU/IOMMU is
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* associated with exactly one stream ID.
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*/
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uint32_t _streamId;
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/**
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* The substream ID identifies an "execution context" within a
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* device behind an SMMU/IOMMU. It's intended to map 1-to-1 to
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* PCIe PASID (Process Address Space ID). The presence of a
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* substream ID is optional.
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*/
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uint32_t _substreamId;
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};
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/** The address space ID. */
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uint64_t _asid;
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};
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/** The virtual address of the request. */
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Addr _vaddr;
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/**
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* Extra data for the request, such as the return value of
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* store conditional or the compare value for a CAS. */
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uint64_t _extraData;
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/** The context ID (for statistics, locks, and wakeups). */
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ContextID _contextId;
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/** program counter of initiating access; for tracing/debugging */
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Addr _pc;
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/** Sequence number of the instruction that creates the request */
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InstSeqNum _reqInstSeqNum;
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/** A pointer to an atomic operation */
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AtomicOpFunctor *atomicOpFunctor;
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public:
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/**
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* Minimal constructor. No fields are initialized. (Note that
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* _flags and privateFlags are cleared by Flags default
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* constructor.)
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*/
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Request()
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _pc(0),
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_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{}
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Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
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InstSeqNum seq_num, ContextID cid)
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _pc(0),
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_reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{
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setPhys(paddr, size, flags, mid, curTick());
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setContext(cid);
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privateFlags.set(VALID_INST_SEQ_NUM);
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}
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/**
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* Constructor for physical (e.g. device) requests. Initializes
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* just physical address, size, flags, and timestamp (to curTick()).
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* These fields are adequate to perform a request.
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*/
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Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _pc(0),
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_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{
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setPhys(paddr, size, flags, mid, curTick());
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}
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Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _pc(0),
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_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{
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setPhys(paddr, size, flags, mid, time);
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}
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Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time,
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Addr pc)
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _pc(pc),
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_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{
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setPhys(paddr, size, flags, mid, time);
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privateFlags.set(VALID_PC);
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}
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Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
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MasterID mid, Addr pc, ContextID cid)
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _pc(0),
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_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{
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setVirt(asid, vaddr, size, flags, mid, pc);
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setContext(cid);
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}
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Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
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MasterID mid, Addr pc, ContextID cid,
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AtomicOpFunctor *atomic_op)
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{
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setVirt(asid, vaddr, size, flags, mid, pc, atomic_op);
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setContext(cid);
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}
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Request(const Request& other)
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: _paddr(other._paddr), _size(other._size),
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_masterId(other._masterId),
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_flags(other._flags),
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_memSpaceConfigFlags(other._memSpaceConfigFlags),
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privateFlags(other.privateFlags),
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_time(other._time),
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_taskId(other._taskId), _asid(other._asid), _vaddr(other._vaddr),
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_extraData(other._extraData), _contextId(other._contextId),
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_pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum),
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translateDelta(other.translateDelta),
|
|
accessDelta(other.accessDelta), depth(other.depth)
|
|
{
|
|
if (other.atomicOpFunctor)
|
|
atomicOpFunctor = (other.atomicOpFunctor)->clone();
|
|
else
|
|
atomicOpFunctor = nullptr;
|
|
}
|
|
|
|
~Request()
|
|
{
|
|
if (hasAtomicOpFunctor()) {
|
|
delete atomicOpFunctor;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Set up Context numbers.
|
|
*/
|
|
void
|
|
setContext(ContextID context_id)
|
|
{
|
|
_contextId = context_id;
|
|
privateFlags.set(VALID_CONTEXT_ID);
|
|
}
|
|
|
|
void
|
|
setStreamId(uint32_t sid)
|
|
{
|
|
_streamId = sid;
|
|
privateFlags.set(VALID_STREAM_ID);
|
|
}
|
|
|
|
void
|
|
setSubStreamId(uint32_t ssid)
|
|
{
|
|
assert(privateFlags.isSet(VALID_STREAM_ID));
|
|
_substreamId = ssid;
|
|
privateFlags.set(VALID_SUBSTREAM_ID);
|
|
}
|
|
|
|
/**
|
|
* Set up a virtual (e.g., CPU) request in a previously
|
|
* allocated Request object.
|
|
*/
|
|
void
|
|
setVirt(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
|
|
MasterID mid, Addr pc, AtomicOpFunctor *amo_op = nullptr)
|
|
{
|
|
_asid = asid;
|
|
_vaddr = vaddr;
|
|
_size = size;
|
|
_masterId = mid;
|
|
_pc = pc;
|
|
_time = curTick();
|
|
|
|
_flags.clear(~STICKY_FLAGS);
|
|
_flags.set(flags);
|
|
privateFlags.clear(~STICKY_PRIVATE_FLAGS);
|
|
privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
|
|
depth = 0;
|
|
accessDelta = 0;
|
|
translateDelta = 0;
|
|
atomicOpFunctor = amo_op;
|
|
}
|
|
|
|
/**
|
|
* Set just the physical address. This usually used to record the
|
|
* result of a translation. However, when using virtualized CPUs
|
|
* setPhys() is sometimes called to finalize a physical address
|
|
* without a virtual address, so we can't check if the virtual
|
|
* address is valid.
|
|
*/
|
|
void
|
|
setPaddr(Addr paddr)
|
|
{
|
|
_paddr = paddr;
|
|
privateFlags.set(VALID_PADDR);
|
|
}
|
|
|
|
/**
|
|
* Generate two requests as if this request had been split into two
|
|
* pieces. The original request can't have been translated already.
|
|
*/
|
|
// TODO: this function is still required by TimingSimpleCPU - should be
|
|
// removed once TimingSimpleCPU will support arbitrarily long multi-line
|
|
// mem. accesses
|
|
void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
|
|
{
|
|
assert(privateFlags.isSet(VALID_VADDR));
|
|
assert(privateFlags.noneSet(VALID_PADDR));
|
|
assert(split_addr > _vaddr && split_addr < _vaddr + _size);
|
|
req1 = std::make_shared<Request>(*this);
|
|
req2 = std::make_shared<Request>(*this);
|
|
req1->_size = split_addr - _vaddr;
|
|
req2->_vaddr = split_addr;
|
|
req2->_size = _size - req1->_size;
|
|
if (!_byteEnable.empty()) {
|
|
req1->_byteEnable = std::vector<bool>(
|
|
_byteEnable.begin(),
|
|
_byteEnable.begin() + req1->_size);
|
|
req2->_byteEnable = std::vector<bool>(
|
|
_byteEnable.begin() + req1->_size,
|
|
_byteEnable.end());
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Accessor for paddr.
|
|
*/
|
|
bool
|
|
hasPaddr() const
|
|
{
|
|
return privateFlags.isSet(VALID_PADDR);
|
|
}
|
|
|
|
Addr
|
|
getPaddr() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_PADDR));
|
|
return _paddr;
|
|
}
|
|
|
|
/**
|
|
* Time for the TLB/table walker to successfully translate this request.
|
|
*/
|
|
Tick translateDelta;
|
|
|
|
/**
|
|
* Access latency to complete this memory transaction not including
|
|
* translation time.
|
|
*/
|
|
Tick accessDelta;
|
|
|
|
/**
|
|
* Level of the cache hierachy where this request was responded to
|
|
* (e.g. 0 = L1; 1 = L2).
|
|
*/
|
|
mutable int depth;
|
|
|
|
/**
|
|
* Accessor for size.
|
|
*/
|
|
bool
|
|
hasSize() const
|
|
{
|
|
return privateFlags.isSet(VALID_SIZE);
|
|
}
|
|
|
|
unsigned
|
|
getSize() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_SIZE));
|
|
return _size;
|
|
}
|
|
|
|
const std::vector<bool>&
|
|
getByteEnable() const
|
|
{
|
|
return _byteEnable;
|
|
}
|
|
|
|
void
|
|
setByteEnable(const std::vector<bool>& be)
|
|
{
|
|
assert(be.empty() || be.size() == _size);
|
|
_byteEnable = be;
|
|
}
|
|
|
|
/** Accessor for time. */
|
|
Tick
|
|
time() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
|
|
return _time;
|
|
}
|
|
|
|
/**
|
|
* Accessor for atomic-op functor.
|
|
*/
|
|
bool
|
|
hasAtomicOpFunctor()
|
|
{
|
|
return atomicOpFunctor != NULL;
|
|
}
|
|
|
|
AtomicOpFunctor *
|
|
getAtomicOpFunctor()
|
|
{
|
|
assert(atomicOpFunctor != NULL);
|
|
return atomicOpFunctor;
|
|
}
|
|
|
|
/** Accessor for flags. */
|
|
Flags
|
|
getFlags()
|
|
{
|
|
assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
|
|
return _flags;
|
|
}
|
|
|
|
/** Note that unlike other accessors, this function sets *specific
|
|
flags* (ORs them in); it does not assign its argument to the
|
|
_flags field. Thus this method should rightly be called
|
|
setFlags() and not just flags(). */
|
|
void
|
|
setFlags(Flags flags)
|
|
{
|
|
assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
|
|
_flags.set(flags);
|
|
}
|
|
|
|
void
|
|
setMemSpaceConfigFlags(MemSpaceConfigFlags extraFlags)
|
|
{
|
|
assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR));
|
|
_memSpaceConfigFlags.set(extraFlags);
|
|
}
|
|
|
|
/** Accessor function for vaddr.*/
|
|
bool
|
|
hasVaddr() const
|
|
{
|
|
return privateFlags.isSet(VALID_VADDR);
|
|
}
|
|
|
|
Addr
|
|
getVaddr() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_VADDR));
|
|
return _vaddr;
|
|
}
|
|
|
|
/** Accesssor for the requestor id. */
|
|
MasterID
|
|
masterId() const
|
|
{
|
|
return _masterId;
|
|
}
|
|
|
|
uint32_t
|
|
taskId() const
|
|
{
|
|
return _taskId;
|
|
}
|
|
|
|
void
|
|
taskId(uint32_t id) {
|
|
_taskId = id;
|
|
}
|
|
|
|
/** Accessor function for asid.*/
|
|
uint64_t
|
|
getAsid() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_VADDR));
|
|
return _asid;
|
|
}
|
|
|
|
/** Accessor function for asid.*/
|
|
void
|
|
setAsid(uint64_t asid)
|
|
{
|
|
_asid = asid;
|
|
}
|
|
|
|
/** Accessor function for architecture-specific flags.*/
|
|
ArchFlagsType
|
|
getArchFlags() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
|
|
return _flags & ARCH_BITS;
|
|
}
|
|
|
|
/** Accessor function to check if sc result is valid. */
|
|
bool
|
|
extraDataValid() const
|
|
{
|
|
return privateFlags.isSet(VALID_EXTRA_DATA);
|
|
}
|
|
|
|
/** Accessor function for store conditional return value.*/
|
|
uint64_t
|
|
getExtraData() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_EXTRA_DATA));
|
|
return _extraData;
|
|
}
|
|
|
|
/** Accessor function for store conditional return value.*/
|
|
void
|
|
setExtraData(uint64_t extraData)
|
|
{
|
|
_extraData = extraData;
|
|
privateFlags.set(VALID_EXTRA_DATA);
|
|
}
|
|
|
|
bool
|
|
hasContextId() const
|
|
{
|
|
return privateFlags.isSet(VALID_CONTEXT_ID);
|
|
}
|
|
|
|
/** Accessor function for context ID.*/
|
|
ContextID
|
|
contextId() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_CONTEXT_ID));
|
|
return _contextId;
|
|
}
|
|
|
|
uint32_t
|
|
streamId() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_STREAM_ID));
|
|
return _streamId;
|
|
}
|
|
|
|
bool
|
|
hasSubstreamId() const
|
|
{
|
|
return privateFlags.isSet(VALID_SUBSTREAM_ID);
|
|
}
|
|
|
|
uint32_t
|
|
substreamId() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_SUBSTREAM_ID));
|
|
return _substreamId;
|
|
}
|
|
|
|
void
|
|
setPC(Addr pc)
|
|
{
|
|
privateFlags.set(VALID_PC);
|
|
_pc = pc;
|
|
}
|
|
|
|
bool
|
|
hasPC() const
|
|
{
|
|
return privateFlags.isSet(VALID_PC);
|
|
}
|
|
|
|
/** Accessor function for pc.*/
|
|
Addr
|
|
getPC() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_PC));
|
|
return _pc;
|
|
}
|
|
|
|
/**
|
|
* Increment/Get the depth at which this request is responded to.
|
|
* This currently happens when the request misses in any cache level.
|
|
*/
|
|
void incAccessDepth() const { depth++; }
|
|
int getAccessDepth() const { return depth; }
|
|
|
|
/**
|
|
* Set/Get the time taken for this request to be successfully translated.
|
|
*/
|
|
void setTranslateLatency() { translateDelta = curTick() - _time; }
|
|
Tick getTranslateLatency() const { return translateDelta; }
|
|
|
|
/**
|
|
* Set/Get the time taken to complete this request's access, not including
|
|
* the time to successfully translate the request.
|
|
*/
|
|
void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
|
|
Tick getAccessLatency() const { return accessDelta; }
|
|
|
|
/**
|
|
* Accessor for the sequence number of instruction that creates the
|
|
* request.
|
|
*/
|
|
bool
|
|
hasInstSeqNum() const
|
|
{
|
|
return privateFlags.isSet(VALID_INST_SEQ_NUM);
|
|
}
|
|
|
|
InstSeqNum
|
|
getReqInstSeqNum() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_INST_SEQ_NUM));
|
|
return _reqInstSeqNum;
|
|
}
|
|
|
|
void
|
|
setReqInstSeqNum(const InstSeqNum seq_num)
|
|
{
|
|
privateFlags.set(VALID_INST_SEQ_NUM);
|
|
_reqInstSeqNum = seq_num;
|
|
}
|
|
|
|
/** Accessor functions for flags. Note that these are for testing
|
|
only; setting flags should be done via setFlags(). */
|
|
bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
|
|
bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
|
|
bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
|
|
bool isPrefetch() const { return (_flags.isSet(PREFETCH) ||
|
|
_flags.isSet(PF_EXCLUSIVE)); }
|
|
bool isPrefetchEx() const { return _flags.isSet(PF_EXCLUSIVE); }
|
|
bool isLLSC() const { return _flags.isSet(LLSC); }
|
|
bool isPriv() const { return _flags.isSet(PRIVILEGED); }
|
|
bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
|
|
bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
|
|
bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
|
|
bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
|
|
bool isSecure() const { return _flags.isSet(SECURE); }
|
|
bool isPTWalk() const { return _flags.isSet(PT_WALK); }
|
|
bool isAcquire() const { return _flags.isSet(ACQUIRE); }
|
|
bool isRelease() const { return _flags.isSet(RELEASE); }
|
|
bool isKernel() const { return _flags.isSet(KERNEL); }
|
|
bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
|
|
bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }
|
|
|
|
bool
|
|
isAtomic() const
|
|
{
|
|
return _flags.isSet(ATOMIC_RETURN_OP) ||
|
|
_flags.isSet(ATOMIC_NO_RETURN_OP);
|
|
}
|
|
|
|
/**
|
|
* Accessor functions for the destination of a memory request. The
|
|
* destination flag can specify a point of reference for the
|
|
* operation (e.g. a cache block clean to the the point of
|
|
* unification). At the moment the destination is only used by the
|
|
* cache maintenance operations.
|
|
*/
|
|
bool isToPOU() const { return _flags.isSet(DST_POU); }
|
|
bool isToPOC() const { return _flags.isSet(DST_POC); }
|
|
Flags getDest() const { return _flags & DST_BITS; }
|
|
|
|
/**
|
|
* Accessor functions for the memory space configuration flags and used by
|
|
* GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
|
|
* these are for testing only; setting extraFlags should be done via
|
|
* setMemSpaceConfigFlags().
|
|
*/
|
|
bool isScoped() const { return _memSpaceConfigFlags.isSet(SCOPE_VALID); }
|
|
|
|
bool
|
|
isWavefrontScope() const
|
|
{
|
|
assert(isScoped());
|
|
return _memSpaceConfigFlags.isSet(WAVEFRONT_SCOPE);
|
|
}
|
|
|
|
bool
|
|
isWorkgroupScope() const
|
|
{
|
|
assert(isScoped());
|
|
return _memSpaceConfigFlags.isSet(WORKGROUP_SCOPE);
|
|
}
|
|
|
|
bool
|
|
isDeviceScope() const
|
|
{
|
|
assert(isScoped());
|
|
return _memSpaceConfigFlags.isSet(DEVICE_SCOPE);
|
|
}
|
|
|
|
bool
|
|
isSystemScope() const
|
|
{
|
|
assert(isScoped());
|
|
return _memSpaceConfigFlags.isSet(SYSTEM_SCOPE);
|
|
}
|
|
|
|
bool
|
|
isGlobalSegment() const
|
|
{
|
|
return _memSpaceConfigFlags.isSet(GLOBAL_SEGMENT) ||
|
|
(!isGroupSegment() && !isPrivateSegment() &&
|
|
!isKernargSegment() && !isReadonlySegment() &&
|
|
!isSpillSegment() && !isArgSegment());
|
|
}
|
|
|
|
bool
|
|
isGroupSegment() const
|
|
{
|
|
return _memSpaceConfigFlags.isSet(GROUP_SEGMENT);
|
|
}
|
|
|
|
bool
|
|
isPrivateSegment() const
|
|
{
|
|
return _memSpaceConfigFlags.isSet(PRIVATE_SEGMENT);
|
|
}
|
|
|
|
bool
|
|
isKernargSegment() const
|
|
{
|
|
return _memSpaceConfigFlags.isSet(KERNARG_SEGMENT);
|
|
}
|
|
|
|
bool
|
|
isReadonlySegment() const
|
|
{
|
|
return _memSpaceConfigFlags.isSet(READONLY_SEGMENT);
|
|
}
|
|
|
|
bool
|
|
isSpillSegment() const
|
|
{
|
|
return _memSpaceConfigFlags.isSet(SPILL_SEGMENT);
|
|
}
|
|
|
|
bool
|
|
isArgSegment() const
|
|
{
|
|
return _memSpaceConfigFlags.isSet(ARG_SEGMENT);
|
|
}
|
|
|
|
/**
|
|
* Accessor functions to determine whether this request is part of
|
|
* a cache maintenance operation. At the moment three operations
|
|
* are supported:
|
|
|
|
* 1) A cache clean operation updates all copies of a memory
|
|
* location to the point of reference,
|
|
* 2) A cache invalidate operation invalidates all copies of the
|
|
* specified block in the memory above the point of reference,
|
|
* 3) A clean and invalidate operation is a combination of the two
|
|
* operations.
|
|
* @{ */
|
|
bool isCacheClean() const { return _flags.isSet(CLEAN); }
|
|
bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
|
|
bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
|
|
/** @} */
|
|
};
|
|
|
|
#endif // __MEM_REQUEST_HH__
|