6687265fe2
Change-Id: Icfba8e23b5f6820a6ddefe1a50abbe5f8825b7b5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25444 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
230 lines
7.5 KiB
C++
230 lines
7.5 KiB
C++
/*
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* Copyright (c) 2011, 2016-2017 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_COMM_HH__
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#define __CPU_O3_COMM_HH__
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#include <vector>
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#include "arch/types.hh"
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#include "base/types.hh"
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#include "cpu/inst_seq.hh"
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#include "sim/faults.hh"
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/** Struct that defines the information passed from fetch to decode. */
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template<class Impl>
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struct DefaultFetchDefaultDecode {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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Fault fetchFault;
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InstSeqNum fetchFaultSN;
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bool clearFetchFault;
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};
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/** Struct that defines the information passed from decode to rename. */
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template<class Impl>
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struct DefaultDecodeDefaultRename {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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/** Struct that defines the information passed from rename to IEW. */
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template<class Impl>
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struct DefaultRenameDefaultIEW {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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/** Struct that defines the information passed from IEW to commit. */
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template<class Impl>
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struct DefaultIEWDefaultCommit {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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DynInstPtr mispredictInst[Impl::MaxThreads];
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Addr mispredPC[Impl::MaxThreads];
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InstSeqNum squashedSeqNum[Impl::MaxThreads];
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TheISA::PCState pc[Impl::MaxThreads];
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bool squash[Impl::MaxThreads];
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bool branchMispredict[Impl::MaxThreads];
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bool branchTaken[Impl::MaxThreads];
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bool includeSquashInst[Impl::MaxThreads];
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};
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template<class Impl>
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struct IssueStruct {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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/** Struct that defines all backwards communication. */
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template<class Impl>
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struct TimeBufStruct {
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typedef typename Impl::DynInstPtr DynInstPtr;
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struct decodeComm {
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TheISA::PCState nextPC;
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DynInstPtr mispredictInst;
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DynInstPtr squashInst;
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InstSeqNum doneSeqNum;
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Addr mispredPC;
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uint64_t branchAddr;
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unsigned branchCount;
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bool squash;
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bool predIncorrect;
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bool branchMispredict;
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bool branchTaken;
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};
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decodeComm decodeInfo[Impl::MaxThreads];
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struct renameComm {
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};
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renameComm renameInfo[Impl::MaxThreads];
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struct iewComm {
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// Also eventually include skid buffer space.
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unsigned freeIQEntries;
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unsigned freeLQEntries;
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unsigned freeSQEntries;
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unsigned dispatchedToLQ;
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unsigned dispatchedToSQ;
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unsigned iqCount;
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unsigned ldstqCount;
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unsigned dispatched;
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bool usedIQ;
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bool usedLSQ;
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};
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iewComm iewInfo[Impl::MaxThreads];
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struct commitComm {
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/////////////////////////////////////////////////////////////////////
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// This code has been re-structured for better packing of variables
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// instead of by stage which is the more logical way to arrange the
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// data.
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// F = Fetch
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// D = Decode
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// I = IEW
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// R = Rename
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// As such each member is annotated with who consumes it
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// e.g. bool variable name // *F,R for Fetch and Rename
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/////////////////////////////////////////////////////////////////////
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/// The pc of the next instruction to execute. This is the next
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/// instruction for a branch mispredict, but the same instruction for
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/// order violation and the like
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TheISA::PCState pc; // *F
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/// Provide fetch the instruction that mispredicted, if this
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/// pointer is not-null a misprediction occured
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DynInstPtr mispredictInst; // *F
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/// Instruction that caused the a non-mispredict squash
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DynInstPtr squashInst; // *F
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/// Hack for now to send back a strictly ordered access to the
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/// IEW stage.
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DynInstPtr strictlyOrderedLoad; // *I
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/// Communication specifically to the IQ to tell the IQ that it can
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/// schedule a non-speculative instruction.
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InstSeqNum nonSpecSeqNum; // *I
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/// Represents the instruction that has either been retired or
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/// squashed. Similar to having a single bus that broadcasts the
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/// retired or squashed sequence number.
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InstSeqNum doneSeqNum; // *F, I
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/// Tell Rename how many free entries it has in the ROB
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unsigned freeROBEntries; // *R
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bool squash; // *F, D, R, I
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bool robSquashing; // *F, D, R, I
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/// Rename should re-read number of free rob entries
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bool usedROB; // *R
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/// Notify Rename that the ROB is empty
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bool emptyROB; // *R
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/// Was the branch taken or not
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bool branchTaken; // *F
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/// If an interrupt is pending and fetch should stall
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bool interruptPending; // *F
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/// If the interrupt ended up being cleared before being handled
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bool clearInterrupt; // *F
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/// Hack for now to send back an strictly ordered access to
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/// the IEW stage.
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bool strictlyOrdered; // *I
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};
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commitComm commitInfo[Impl::MaxThreads];
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bool decodeBlock[Impl::MaxThreads];
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bool decodeUnblock[Impl::MaxThreads];
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bool renameBlock[Impl::MaxThreads];
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bool renameUnblock[Impl::MaxThreads];
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bool iewBlock[Impl::MaxThreads];
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bool iewUnblock[Impl::MaxThreads];
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};
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#endif //__CPU_O3_COMM_HH__
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