Tim Harris 44e5e7e053 X86: Obey the wp bit of CR0. ...

If cr0.wp ("write protect" bit) is clear then do not generate page faults when
writing to write-protected pages in kernel mode.

2011-02-07 15:18:52 -08:00

..

alpha

Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.

2011-02-03 21:47:58 -08:00

arm

Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.

2011-02-03 21:47:58 -08:00

generic

ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.

2010-10-31 00:07:20 -07:00

mips

Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.

2011-02-03 21:47:58 -08:00

noisa

SCons: Support building without an ISA

2010-11-19 18:00:39 -06:00

power

Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.

2011-02-03 21:47:58 -08:00

sparc

Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.

2011-02-03 21:47:58 -08:00

x86

X86: Obey the wp bit of CR0.

2011-02-07 15:18:52 -08:00

isa_parser.py

scons: show sources and targets when building, and colorize output.

2011-01-07 21:50:13 -08:00

micro_asm_test.py

Add a second section to make sure the ROM is extended properly.

2007-05-31 22:21:21 +00:00

micro_asm.py

scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access

2009-09-22 15:24:16 -07:00

SConscript

scons: show sources and targets when building, and colorize output.

2011-01-07 21:50:13 -08:00