9909ea8a40
DefaultFoo => Foo O3Foo => Foo FullO3CPU => CPU DerivO3CPU => O3CPU (python) DerivO3 => o3::CPU Change-Id: I04551214442633c79c33e9d86b067ff3ec0d1a8d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42120 Maintainer: Gabe Black <gabe.black@gmail.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
77 lines
3.0 KiB
C++
77 lines
3.0 KiB
C++
/*
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* Copyright (c) 2012, 2019 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/o3/thread_state.hh"
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#include "cpu/o3/cpu.hh"
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namespace o3
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{
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ThreadState::ThreadState(CPU *_cpu, int _thread_num, Process *_process) :
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::ThreadState(_cpu, _thread_num, _process),
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comInstEventQueue("instruction-based event queue")
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{}
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void
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ThreadState::serialize(CheckpointOut &cp) const
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{
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::ThreadState::serialize(cp);
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// Use the ThreadContext serialization helper to serialize the
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// TC.
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::serialize(*tc, cp);
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}
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void
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ThreadState::unserialize(CheckpointIn &cp)
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{
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// Prevent squashing - we don't have any instructions in
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// flight that we need to squash since we just instantiated a
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// clean system.
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noSquashFromTC = true;
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::ThreadState::unserialize(cp);
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// Use the ThreadContext serialization helper to unserialize
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// the TC.
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::unserialize(*tc, cp);
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noSquashFromTC = false;
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}
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} // namespace o3
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