ade8c08e7a
Change-Id: Ie843e2b4ab6e506bb195bfcef33cead9a6273901 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50127 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
99 lines
3.9 KiB
Python
99 lines
3.9 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from components_library.boards.mem_mode import MemMode
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from components_library.boards.abstract_board import AbstractBoard
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from components_library.processors.simple_core import SimpleCore
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from components_library.processors.cpu_types import CPUTypes
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from .switchable_processor import SwitchableProcessor
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from ..utils.override import *
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from m5.objects import KvmVM
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class SimpleSwitchableProcessor(SwitchableProcessor):
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"""
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A Simplified implementation of SwitchableProcessor where there is one
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processor at the start of the simuation, and another that can be switched
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to via the "switch" function later in the simulation. This is good for
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fast/detailed CPU setups.
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"""
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def __init__(
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self,
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starting_core_type: CPUTypes,
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switch_core_type: CPUTypes,
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num_cores: int,
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) -> None:
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if num_cores <= 0:
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raise AssertionError("Number of cores must be a positive integer!")
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self._start_key = "start"
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self._switch_key = "switch"
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self._current_is_start = True
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if starting_core_type in (CPUTypes.TIMING, CPUTypes.O3):
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self._mem_mode = MemMode.TIMING
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elif starting_core_type == CPUTypes.KVM:
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self._mem_mode = MemMode.ATOMIC_NONCACHING
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elif starting_core_type == CPUTypes.ATOMIC:
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self._mem_mode = MemMode.ATOMIC
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else:
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raise NotImplementedError
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switchable_cores = {
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self._start_key: [
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SimpleCore(cpu_type=starting_core_type, core_id=i)
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for i in range(num_cores)
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],
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self._switch_key: [
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SimpleCore(cpu_type=switch_core_type, core_id=i)
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for i in range(num_cores)
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],
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}
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super(SimpleSwitchableProcessor, self).__init__(
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switchable_cores=switchable_cores,
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starting_cores=self._start_key,
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)
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@overrides(SwitchableProcessor)
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def incorporate_processor(self, board: AbstractBoard) -> None:
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super().incorporate_processor(board=board)
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board.set_mem_mode(self._mem_mode)
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def switch(self):
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"""Switches to the "switched out" cores."""
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if self._current_is_start:
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self.switch_to_processor(self._switch_key)
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else:
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self.switch_to_processor(self._start_key)
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self._current_is_start = not self._current_is_start
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