Files
gem5/src/sim/SConscript
Anouk Van Laer cc2f48ccfc sim-power: Addition of PowerDomains
PowerDomains group multiple objects together to regulate their power
state. There are 2 types of objects in a PowerDomain: leaders and
followers. The power state of a PowerDomain is the most performant
power state of any of the leaders. The power state of the followers is
determined by the power state of the PowerDomain they belong to: they
need to be in a power state which is more or equally performant to the
power state of the PowerDomain.

Leaders can be ClockedObjects or other PowerDomains. Followers can
only be ClockedObjects. PowerDomains can be be nested but a
PowerDomain can only be a leader of another PowerDomain, NOT a
follower. PowerDomains are not present in the hierarchy by default,
the user needs to create and configure them in the configuration file.

The user can add an hierachy by setting the led_by parameter. gem5
will then create leaders and followers for each domain and calculate
the allowed power states for the domain.

Objects in a PowerDomain need to have at least the ON state in the
possible_states.

An example of a powerDomain config is:

pd = PowerDomain()
cpu0 = BaseCPU()
cpu1 = BaseCPU()
shared_cache = BaseCache()
cache.power_state.led_by = pd
pd.led_by = [cpu0, cpu1]

This will create a PowerDomain, where the CPUs determine their own
power states and the shared cache (via the PowerDomain) follows those
power states (when possible).

Change-Id: I4c4cd01f06d45476c6e0fb2afeb778613733e2ff
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28051
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:03:31 +00:00

129 lines
3.9 KiB
Python

# -*- mode:python -*-
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
SimObject('ClockedObject.py')
SimObject('TickedObject.py')
SimObject('Workload.py')
SimObject('Root.py')
SimObject('ClockDomain.py')
SimObject('VoltageDomain.py')
SimObject('System.py')
SimObject('DVFSHandler.py')
SimObject('SubSystem.py')
SimObject('RedirectPath.py')
SimObject('PowerState.py')
SimObject('PowerDomain.py')
Source('async.cc')
Source('backtrace_%s.cc' % env['BACKTRACE_IMPL'])
Source('core.cc')
Source('tags.cc')
Source('cxx_config.cc')
Source('cxx_manager.cc')
Source('cxx_config_ini.cc')
Source('debug.cc')
Source('py_interact.cc', add_tags='python')
Source('eventq.cc')
Source('global_event.cc')
Source('init.cc', add_tags='python')
Source('init_signals.cc')
Source('main.cc', tags='main')
Source('kernel_workload.cc')
Source('port.cc')
Source('python.cc', add_tags='python')
Source('redirect_path.cc')
Source('root.cc')
Source('serialize.cc')
Source('drain.cc')
Source('sim_events.cc')
Source('sim_object.cc')
Source('sub_system.cc')
Source('ticked_object.cc')
Source('simulate.cc')
Source('stat_control.cc')
Source('stat_register.cc', add_tags='python')
Source('clock_domain.cc')
Source('voltage_domain.cc')
Source('se_signal.cc')
Source('linear_solver.cc')
Source('system.cc')
Source('dvfs_handler.cc')
Source('clocked_object.cc')
Source('mathexpr.cc')
Source('power_state.cc')
Source('power_domain.cc')
GTest('byteswap.test', 'byteswap.test.cc', '../base/types.cc')
GTest('guest_abi.test', 'guest_abi.test.cc')
if env['TARGET_ISA'] != 'null':
SimObject('InstTracer.py')
SimObject('Process.py')
Source('faults.cc')
Source('process.cc')
Source('fd_array.cc')
Source('fd_entry.cc')
Source('mem_state.cc')
Source('pseudo_inst.cc')
Source('syscall_emul.cc')
Source('syscall_desc.cc')
Source('vma.cc')
if env['TARGET_ISA'] != 'x86':
Source('microcode_rom.cc')
DebugFlag('Checkpoint')
DebugFlag('Config')
DebugFlag('CxxConfig')
DebugFlag('Drain')
DebugFlag('Event')
DebugFlag('Fault')
DebugFlag('Flow')
DebugFlag('IPI')
DebugFlag('IPR')
DebugFlag('Interrupt')
DebugFlag('Loader')
DebugFlag('PseudoInst')
DebugFlag('Stack')
DebugFlag('SyscallBase')
DebugFlag('SyscallVerbose')
DebugFlag('TimeSync')
DebugFlag('Thread')
DebugFlag('Timer')
DebugFlag('VtoPhys')
DebugFlag('WorkItems')
DebugFlag('ClockDomain')
DebugFlag('VoltageDomain')
DebugFlag('DVFS')
DebugFlag('Vma')
DebugFlag('PowerDomain')
CompoundFlag('SyscallAll', [ 'SyscallBase', 'SyscallVerbose'])