9779ba2e37
This patch takes a first step in tightening up how we use the data pointer in write packets. A const getter is added for the pointer itself (getConstPtr), and a number of member functions are also made const accordingly. In a range of places throughout the memory system the new member is used. The patch also removes the unused isReadWrite function.
592 lines
20 KiB
C++
592 lines
20 KiB
C++
/*
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* Copyright (c) 2011 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include <list>
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#include <vector>
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#include "arch/isa_traits.hh"
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#include "arch/locked_mem.hh"
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#include "arch/utility.hh"
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#include "config/the_isa.hh"
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#include "cpu/inorder/resources/cache_unit.hh"
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#include "cpu/inorder/resources/fetch_unit.hh"
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#include "cpu/inorder/cpu.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/resource_pool.hh"
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#include "debug/Activity.hh"
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#include "debug/InOrderCachePort.hh"
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#include "debug/InOrderStall.hh"
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#include "debug/RefCount.hh"
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#include "debug/ThreadModel.hh"
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#include "mem/request.hh"
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using namespace std;
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using namespace TheISA;
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using namespace ThePipeline;
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FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
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Cycles res_latency, InOrderCPU *_cpu,
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ThePipeline::Params *params)
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: CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
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instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize)
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{
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for (int tid = 0; tid < MaxThreads; tid++)
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decoder[tid] = new Decoder;
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}
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FetchUnit::~FetchUnit()
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{
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std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
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std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
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while (fetch_it != end_it) {
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delete (*fetch_it)->block;
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delete *fetch_it;
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fetch_it++;
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}
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fetchBuffer.clear();
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std::list<FetchBlock*>::iterator pend_it = pendingFetch.begin();
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std::list<FetchBlock*>::iterator pend_end = pendingFetch.end();
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while (pend_it != pend_end) {
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if ((*pend_it)->block) {
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delete (*pend_it)->block;
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}
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delete *pend_it;
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pend_it++;
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}
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pendingFetch.clear();
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}
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void
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FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
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DynInstPtr inst)
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{
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Addr block_addr = cacheBlockAlign(inst->getMemAddr());
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Addr fetch_addr = inst->getMemAddr();
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unsigned fetch_offset = (fetch_addr - block_addr) / instSize;
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ThreadID tid = inst->readTid();
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TheISA::PCState instPC = inst->pcState();
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DPRINTF(InOrderCachePort, "Creating instruction [sn:%i] w/fetch data @"
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"addr:%08p block:%08p\n", inst->seqNum, fetch_addr, block_addr);
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assert((*fetch_it)->valid);
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TheISA::MachInst *fetchInsts =
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reinterpret_cast<TheISA::MachInst *>((*fetch_it)->block);
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MachInst mach_inst =
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TheISA::gtoh(fetchInsts[fetch_offset]);
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decoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
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assert(decoder[tid]->instReady());
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inst->setStaticInst(decoder[tid]->decode(instPC));
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inst->pcState(instPC);
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}
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void
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FetchUnit::removeAddrDependency(DynInstPtr inst)
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{
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inst->unsetMemAddr();
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}
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ResReqPtr
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FetchUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
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int slot_num, unsigned cmd)
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{
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ScheduleEntry* sched_entry = *inst->curSkedEntry;
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CacheRequest* cache_req = dynamic_cast<CacheRequest*>(reqs[slot_num]);
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if (!inst->validMemAddr()) {
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panic("Mem. Addr. must be set before requesting cache access\n");
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}
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assert(sched_entry->cmd == InitiateFetch);
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DPRINTF(InOrderCachePort,
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"[tid:%i]: Fetch request from [sn:%i] for addr %08p\n",
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inst->readTid(), inst->seqNum, inst->getMemAddr());
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cache_req->setRequest(inst, stage_num, id, slot_num,
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sched_entry->cmd, MemCmd::ReadReq,
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inst->curSkedEntry->idx);
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return cache_req;
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}
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void
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FetchUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
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int acc_size, int flags)
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{
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ThreadID tid = inst->readTid();
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Addr aligned_addr = cacheBlockAlign(inst->getMemAddr());
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if (cache_req->memReq == NULL) {
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cache_req->memReq =
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new Request(tid, aligned_addr, acc_size, flags,
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cpu->instMasterId(), inst->instAddr(), cpu->readCpuId(),
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tid);
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DPRINTF(InOrderCachePort, "[sn:%i] Created memReq @%x, ->%x\n",
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inst->seqNum, &cache_req->memReq, cache_req->memReq);
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}
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}
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std::list<FetchUnit::FetchBlock*>::iterator
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FetchUnit::findBlock(std::list<FetchBlock*> &fetch_blocks, int asid,
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Addr block_addr)
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{
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std::list<FetchBlock*>::iterator fetch_it = fetch_blocks.begin();
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std::list<FetchBlock*>::iterator end_it = fetch_blocks.end();
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while (fetch_it != end_it) {
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if ((*fetch_it)->asid == asid &&
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(*fetch_it)->addr == block_addr) {
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return fetch_it;
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}
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fetch_it++;
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}
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return fetch_it;
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}
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std::list<FetchUnit::FetchBlock*>::iterator
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FetchUnit::findReplacementBlock()
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{
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std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
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std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
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while (fetch_it != end_it) {
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if ((*fetch_it)->cnt == 0) {
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return fetch_it;
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} else {
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DPRINTF(InOrderCachePort, "Block %08p has %i insts pending.\n",
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(*fetch_it)->addr, (*fetch_it)->cnt);
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}
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fetch_it++;
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}
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return fetch_it;
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}
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void
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FetchUnit::markBlockUsed(std::list<FetchBlock*>::iterator block_it)
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{
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// Move block from whatever location it is in fetch buffer
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// to the back (represents most-recently-used location)
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if (block_it != fetchBuffer.end()) {
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FetchBlock *mru_blk = *block_it;
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fetchBuffer.erase(block_it);
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fetchBuffer.push_back(mru_blk);
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}
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}
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int
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FetchUnit::blocksInUse()
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{
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std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
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std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
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int cnt = 0;
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while (fetch_it != end_it) {
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if ((*fetch_it)->cnt > 0)
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cnt++;
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fetch_it++;
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}
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return cnt;
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}
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void
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FetchUnit::clearFetchBuffer()
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{
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std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
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std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
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while (fetch_it != end_it) {
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if ((*fetch_it)->block) {
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delete [] (*fetch_it)->block;
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}
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delete *fetch_it;
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fetch_it++;
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}
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fetchBuffer.clear();
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}
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void
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FetchUnit::execute(int slot_num)
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{
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CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(reqs[slot_num]);
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assert(cache_req);
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if (cachePortBlocked && cache_req->cmd == InitiateFetch) {
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DPRINTF(InOrderCachePort, "Cache Port Blocked. Cannot Access\n");
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cache_req->done(false);
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return;
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}
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DynInstPtr inst = cache_req->inst;
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ThreadID tid = inst->readTid();
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Addr block_addr = cacheBlockAlign(inst->getMemAddr());
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int asid = cpu->asid[tid];
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if (inst->fault != NoFault) {
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
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"next stage.\n", tid, inst->seqNum, inst->fault->name(),
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cacheBlockAlign(inst->getMemAddr()));
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finishCacheUnitReq(inst, cache_req);
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return;
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}
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switch (cache_req->cmd)
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{
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case InitiateFetch:
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{
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// Check to see if we've already got this request buffered
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// or pending to be buffered
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bool do_fetch = true;
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int total_pending = pendingFetch.size() + blocksInUse();
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std::list<FetchBlock*>::iterator pending_it;
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pending_it = findBlock(pendingFetch, asid, block_addr);
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if (pending_it != pendingFetch.end()) {
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(*pending_it)->cnt++;
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do_fetch = false;
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DPRINTF(InOrderCachePort, "%08p is a pending fetch block "
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"(pending:%i).\n", block_addr,
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(*pending_it)->cnt);
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} else if (total_pending < fetchBuffSize) {
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std::list<FetchBlock*>::iterator buff_it;
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buff_it = findBlock(fetchBuffer, asid, block_addr);
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if (buff_it != fetchBuffer.end()) {
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(*buff_it)->cnt++;
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do_fetch = false;
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DPRINTF(InOrderCachePort, "%08p is in fetch buffer "
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"(pending:%i).\n", block_addr, (*buff_it)->cnt);
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}
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}
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if (!do_fetch) {
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DPRINTF(InOrderCachePort, "Inst. [sn:%i] marked to be filled "
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"through fetch buffer.\n", inst->seqNum);
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cache_req->fetchBufferFill = true;
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cache_req->setCompleted(true);
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return;
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}
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// Check to see if there is room in the fetchbuffer for this instruction.
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// If not, block this request.
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if (total_pending >= fetchBuffSize) {
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DPRINTF(InOrderCachePort, "No room available in fetch buffer.\n");
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cache_req->done(false);
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return;
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}
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doTLBAccess(inst, cache_req, cacheBlkSize, Request::INST_FETCH, TheISA::TLB::Execute);
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if (inst->fault == NoFault) {
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DPRINTF(InOrderCachePort,
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"[tid:%u]: Initiating fetch access to %s for "
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"addr:%#x (block:%#x)\n", tid, name(),
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cache_req->inst->getMemAddr(), block_addr);
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cache_req->reqData = new uint8_t[cacheBlkSize];
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inst->setCurResSlot(slot_num);
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doCacheAccess(inst);
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if (cache_req->isMemAccPending()) {
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pendingFetch.push_back(new FetchBlock(asid, block_addr));
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// mark replacement block
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}
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}
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break;
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}
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case CompleteFetch:
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if (inst->fault != NoFault) {
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
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"next stage.\n", tid, inst->seqNum, inst->fault->name(),
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inst->getMemAddr());
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finishCacheUnitReq(inst, cache_req);
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return;
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}
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if (cache_req->fetchBufferFill) {
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// Block request if it's depending on a previous fetch, but it hasnt made it yet
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std::list<FetchBlock*>::iterator fetch_it = findBlock(fetchBuffer, asid, block_addr);
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if (fetch_it == fetchBuffer.end()) {
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DPRINTF(InOrderCachePort, "%#x not available yet\n",
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block_addr);
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cache_req->setCompleted(false);
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return;
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}
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// Make New Instruction
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createMachInst(fetch_it, inst);
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if (inst->traceData) {
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inst->traceData->setStaticInst(inst->staticInst);
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inst->traceData->setPC(inst->pcState());
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}
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// FetchBuffer Book-Keeping
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(*fetch_it)->cnt--;
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assert((*fetch_it)->cnt >= 0);
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markBlockUsed(fetch_it);
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cache_req->done();
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return;
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}
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if (cache_req->isMemAccComplete()) {
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if (fetchBuffer.size() >= fetchBuffSize) {
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// If there is no replacement block, then we'll just have
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// to wait till that gets cleared before satisfying the fetch
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// for this instruction
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std::list<FetchBlock*>::iterator repl_it =
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findReplacementBlock();
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if (repl_it == fetchBuffer.end()) {
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DPRINTF(InOrderCachePort, "Unable to find replacement block"
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" and complete fetch.\n");
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cache_req->setCompleted(false);
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return;
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}
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delete [] (*repl_it)->block;
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delete *repl_it;
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fetchBuffer.erase(repl_it);
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}
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DPRINTF(InOrderCachePort,
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"[tid:%i]: Completing Fetch Access for [sn:%i]\n",
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tid, inst->seqNum);
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// Make New Instruction
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std::list<FetchBlock*>::iterator fetch_it =
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findBlock(pendingFetch, asid, block_addr);
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assert(fetch_it != pendingFetch.end());
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assert((*fetch_it)->valid);
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createMachInst(fetch_it, inst);
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if (inst->traceData) {
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inst->traceData->setStaticInst(inst->staticInst);
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inst->traceData->setPC(inst->pcState());
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}
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// Update instructions waiting on new fetch block
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FetchBlock *new_block = (*fetch_it);
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new_block->cnt--;
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assert(new_block->cnt >= 0);
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// Finally, update FetchBuffer w/Pending Block into the
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// MRU location
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pendingFetch.erase(fetch_it);
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fetchBuffer.push_back(new_block);
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DPRINTF(InOrderCachePort, "[tid:%i]: Instruction [sn:%i] is: %s\n",
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tid, inst->seqNum,
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inst->staticInst->disassemble(inst->instAddr()));
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inst->unsetMemAddr();
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cache_req->done();
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} else {
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: Unable to Complete Fetch Access\n",
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tid, inst->seqNum);
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DPRINTF(InOrderStall,
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"STALL: [tid:%i]: Fetch miss from %08p\n",
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tid, cache_req->inst->instAddr());
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cache_req->setCompleted(false);
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// NOTE: For SwitchOnCacheMiss ThreadModel, we *don't* switch on
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// fetch miss, but we could ...
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// cache_req->setMemStall(true);
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}
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break;
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default:
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fatal("Unrecognized command to %s", resName);
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}
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}
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void
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FetchUnit::processCacheCompletion(PacketPtr pkt)
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{
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// Cast to correct packet type
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// @todo: use pkt Sender state here to be consistent with other
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// cpu models
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CacheReqPacket* cache_pkt = dynamic_cast<CacheReqPacket*>(pkt);
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assert(cache_pkt);
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DPRINTF(InOrderCachePort, "Finished request for %x\n",
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cache_pkt->getAddr());
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if (processSquash(cache_pkt))
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return;
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Addr block_addr = cacheBlockAlign(cache_pkt->cacheReq->
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getInst()->getMemAddr());
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DPRINTF(InOrderCachePort,
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"[tid:%u]: [sn:%i]: Waking from fetch access to addr:%#x(phys:%#x), size:%i\n",
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cache_pkt->cacheReq->getInst()->readTid(),
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cache_pkt->cacheReq->getInst()->seqNum,
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block_addr, cache_pkt->getAddr(), cache_pkt->getSize());
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// Cast to correct request type
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CacheRequest *cache_req = dynamic_cast<CacheReqPtr>(
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findRequest(cache_pkt->cacheReq->getInst(), cache_pkt->instIdx));
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if (!cache_req) {
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panic("[tid:%u]: [sn:%i]: Can't find slot for fetch access to "
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"addr. %08p\n", cache_pkt->cacheReq->getInst()->readTid(),
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cache_pkt->cacheReq->getInst()->seqNum,
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block_addr);
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}
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// Get resource request info
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unsigned stage_num = cache_req->getStageNum();
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DynInstPtr inst = cache_req->inst;
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ThreadID tid = cache_req->inst->readTid();
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short asid = cpu->asid[tid];
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assert(!cache_req->isSquashed());
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assert(inst->curSkedEntry->cmd == CompleteFetch);
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DPRINTF(InOrderCachePort,
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"[tid:%u]: [sn:%i]: Processing fetch access for block %#x\n",
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tid, inst->seqNum, block_addr);
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std::list<FetchBlock*>::iterator pend_it = findBlock(pendingFetch, asid,
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block_addr);
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assert(pend_it != pendingFetch.end());
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// Copy Data to pendingFetch queue...
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(*pend_it)->block = new uint8_t[cacheBlkSize];
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memcpy((*pend_it)->block, cache_pkt->getConstPtr<uint8_t>(), cacheBlkSize);
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(*pend_it)->valid = true;
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cache_req->setMemAccPending(false);
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cache_req->setMemAccCompleted();
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|
|
if (cache_req->isMemStall() &&
|
|
cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
|
|
DPRINTF(InOrderCachePort, "[tid:%u] Waking up from Cache Miss.\n",
|
|
tid);
|
|
|
|
cpu->activateContext(tid);
|
|
|
|
DPRINTF(ThreadModel, "Activating [tid:%i] after return from cache"
|
|
"miss.\n", tid);
|
|
}
|
|
|
|
// Wake up the CPU (if it went to sleep and was waiting on this
|
|
// completion event).
|
|
cpu->wakeCPU();
|
|
|
|
DPRINTF(Activity, "[tid:%u] Activating %s due to cache completion\n",
|
|
tid, cpu->pipelineStage[stage_num]->name());
|
|
|
|
cpu->switchToActive(stage_num);
|
|
}
|
|
|
|
void
|
|
FetchUnit::squashCacheRequest(CacheReqPtr req_ptr)
|
|
{
|
|
DynInstPtr inst = req_ptr->getInst();
|
|
ThreadID tid = inst->readTid();
|
|
Addr block_addr = cacheBlockAlign(inst->getMemAddr());
|
|
int asid = cpu->asid[tid];
|
|
|
|
// Check Fetch Buffer (or pending fetch) for this block and
|
|
// update pending counts
|
|
std::list<FetchBlock*>::iterator buff_it = findBlock(fetchBuffer,
|
|
asid,
|
|
block_addr);
|
|
if (buff_it != fetchBuffer.end()) {
|
|
(*buff_it)->cnt--;
|
|
DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Access "
|
|
"for Fetch Buffer block %08p (cnt=%i)\n", inst->seqNum,
|
|
block_addr, (*buff_it)->cnt);
|
|
assert((*buff_it)->cnt >= 0);
|
|
} else {
|
|
std::list<FetchBlock*>::iterator block_it = findBlock(pendingFetch,
|
|
asid,
|
|
block_addr);
|
|
if (block_it != pendingFetch.end()) {
|
|
(*block_it)->cnt--;
|
|
DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Access "
|
|
"for Pending Buffer Block %08p (cnt=%i)\n",
|
|
inst->seqNum,
|
|
block_addr, (*block_it)->cnt);
|
|
assert((*block_it)->cnt >= 0);
|
|
if ((*block_it)->cnt == 0) {
|
|
if ((*block_it)->block) {
|
|
delete [] (*block_it)->block;
|
|
}
|
|
delete *block_it;
|
|
pendingFetch.erase(block_it);
|
|
}
|
|
}
|
|
}
|
|
|
|
CacheUnit::squashCacheRequest(req_ptr);
|
|
}
|
|
|
|
void
|
|
FetchUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
|
|
{
|
|
//@todo: per thread?
|
|
decoder[tid]->reset();
|
|
|
|
//@todo: squash using dummy inst seq num
|
|
squash(NULL, NumStages - 1, 0, tid);
|
|
|
|
//@todo: make sure no blocks are in use
|
|
assert(blocksInUse() == 0);
|
|
assert(pendingFetch.size() == 0);
|
|
|
|
//@todo: clear pendingFetch and fetchBuffer
|
|
clearFetchBuffer();
|
|
}
|