There are several parts to this PR to work towards #1349 . (1) Make RubySystem::getBlockSizeBytes non-static by providing ways to access the block size or passing the block size explicitly to classes. The main changes are: - DataBlocks must be explicitly allocated. A default ctor still exists to avoid needing to heavily modify SLICC. The size can be set using a realloc function, operator=, or copy ctor. This is handled completely transparently meaning no protocol or config changes are required. - WriteMask now requires block size to be set. This is also handled transparently by modifying the SLICC parser to identify WriteMask types and call setBlockSize(). - AbstractCacheEntry and TBE classes now require block size to be set. This is handled transparently by modifying the SLICC parser to identify these classes and call initBlockSize() which calls setBlockSize() for any DataBlock or WriteMask. - All AbstractControllers now have a pointer to RubySystem. This is assigned in SLICC generated code and requires no changes to protocol or configs. - The Ruby Message class now requires block size in all constructors. This is added to the argument list automatically by the SLICC parser. (2) Relax dependence on common functions in src/mem/ruby/common/Address.hh so that RubySystem::getBlockSizeBits is no longer static. Many classes already have a way to get block size from the previous commit, so they simply multiple by 8 to get the number of bits. For handling SLICC and reducing the number of changes, define makeCacheLine, getOffset, etc. in RubyPort and AbstractController. The only protocol changes required are to change any "RubySystem::foo()" calls with "m_ruby_system->foo()". For classes which do not have a way to get access to block size but still used makeLineAddress, getOffset, etc., the block size must be passed to that class. This requires some changes to the SimObject interface for two commonly used classes: DirectoryMemory and RubyPrefecther, resulting in user-facing API changes User-facing API changes: - DirectoryMemory and RubyPrefetcher now require the cache line size as a non-optional argument. - RubySequencer SimObjects now require RubySystem as a non-optional argument. - TesterThread in the GPU ruby tester now requires the cache line size as a non-optional argument. (3) Removes static member variables in RubySystem which control randomization, cooldown, and warmup. These are mostly used by the Ruby Network. The network classes are modified to take these former static variables as parameters which are passed to the corresponding method (e.g., enqueue, delayHead, etc.) rather than needing a RubySystem object at all. Change-Id: Ia63c2ad5cf0bf9d1cbdffba5d3a679bb4d3b1220 (4) There are two major SLICC generated static methods: getNumControllers() on each cache controller which returns the number of controllers created by the configs at run time and the functions which access this method, which are MachineType_base_count and MachineType_base_number. These need to be removed to create multiple RubySystem objects otherwise NetDest, version value, and other objects are incorrect. To remove the static requirement, MachineType_base_count and MachineType_base_number are moved to RubySystem. Any class which needs to call these methods must now have a pointer to a RubySystem. To enable that, several changes are made: - RubyRequest and Message now require a RubySystem pointer in the constructor. The pointer is passed to fields in the Message class which require a RubySystem pointer (e.g., NetDest). SLICC is modified to do this automatically. - SLICC structures may now optionally take an "implicit constructor" which can be used to call a non-default constructor for locally defined variables (e.g., temporary variables within SLICC actions). A statement such as "NetDest bcast_dest;" in SLICC will implicitly append a call to the NetDest constructor taking RubySystem, for example. - RubySystem gets passed to Ruby network objects (Network, Topology).
277 lines
9.5 KiB
C++
277 lines
9.5 KiB
C++
/*
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* Copyright (c) 2020 Inria
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* Copyright (c) 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_STRUCTURES_PREFETCHER_HH__
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#define __MEM_RUBY_STRUCTURES_PREFETCHER_HH__
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// Implements Power 4 like prefetching
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#include <bitset>
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#include "base/circular_queue.hh"
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#include "base/statistics.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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#include "mem/ruby/slicc_interface/RubyRequest.hh"
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#include "mem/ruby/system/RubySystem.hh"
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#include "params/RubyPrefetcher.hh"
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#include "sim/sim_object.hh"
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#define MAX_PF_INFLIGHT 8
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namespace gem5
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{
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namespace ruby
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{
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class PrefetchEntry
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{
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public:
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/// constructor
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PrefetchEntry(int block_size)
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{
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// default: 1 cache-line stride
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m_stride = (1 << floorLog2(block_size));
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m_use_time = Cycles(0);
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m_is_valid = false;
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}
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//! The base address for the stream prefetch
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Addr m_address;
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//! stride distance to get next address from
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int m_stride;
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//! the last time that any prefetched request was used
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Cycles m_use_time;
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//! valid bit for each stream
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bool m_is_valid;
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//! L1D prefetches loads and stores
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RubyRequestType m_type;
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//! Bitset for tracking prefetches for which addresses have been
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//! issued, which ones have completed.
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std::bitset<MAX_PF_INFLIGHT> requestIssued;
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std::bitset<MAX_PF_INFLIGHT> requestCompleted;
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};
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class RubyPrefetcher : public SimObject
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{
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public:
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typedef RubyPrefetcherParams Params;
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RubyPrefetcher(const Params &p);
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~RubyPrefetcher() = default;
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void issueNextPrefetch(Addr address, PrefetchEntry *stream);
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/**
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* Implement the prefetch hit(miss) callback interface.
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* These functions are called by the cache when it hits(misses)
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* on a line with the line's prefetch bit set. If this address
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* hits in m_array we will continue prefetching the stream.
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*/
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void observePfHit(Addr address);
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void observePfMiss(Addr address);
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/**
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* Observe a memory miss from the cache.
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*
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* @param address The physical address that missed out of the cache.
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*/
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void observeMiss(Addr address, const RubyRequestType& type);
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/**
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* Print out some statistics
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*/
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void print(std::ostream& out) const;
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void setController(AbstractController *_ctrl)
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{ m_controller = _ctrl; }
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private:
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struct UnitFilterEntry
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{
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/** Address to which this filter entry refers. */
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Addr addr;
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/** Counter of the number of times this entry has been hit. */
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uint32_t hits;
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UnitFilterEntry(Addr _addr = 0)
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: addr(_addr), hits(0)
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{
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}
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};
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struct NonUnitFilterEntry : public UnitFilterEntry
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{
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/** Stride (in # of cache lines). */
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int stride;
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NonUnitFilterEntry(Addr _addr = 0)
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: UnitFilterEntry(_addr), stride(0)
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{
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}
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void
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clear()
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{
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addr = 0;
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stride = 0;
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hits = 0;
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}
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};
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/**
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* Returns an unused stream buffer (or if all are used, returns the
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* least recently used (accessed) stream buffer).
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* @return The index of the least recently used stream buffer.
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*/
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uint32_t getLRUindex(void);
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//! allocate a new stream buffer at a specific index
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void initializeStream(Addr address, int stride,
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uint32_t index, const RubyRequestType& type);
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//! get pointer to the matching stream entry, returns NULL if not found
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//! index holds the multiple of the stride this address is.
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PrefetchEntry* getPrefetchEntry(Addr address,
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uint32_t &index);
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/**
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* Access a unit stride filter to determine if there is a hit, and
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* update it otherwise.
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*
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* @param filter Unit filter being accessed.
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* @param line_addr Address being accessed, block aligned.
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* @param stride The stride value.
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* @param type Type of the request that generated the access.
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* @return True if a corresponding entry was found.
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*/
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bool accessUnitFilter(CircularQueue<UnitFilterEntry>* const filter,
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Addr line_addr, int stride, const RubyRequestType& type);
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/**
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* Access a non-unit stride filter to determine if there is a hit, and
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* update it otherwise.
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*
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* @param line_addr Address being accessed, block aligned.
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* @param type Type of the request that generated the access.
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* @return True if a corresponding entry was found and its stride is
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* not zero.
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*/
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bool accessNonunitFilter(Addr line_addr, const RubyRequestType& type);
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/// determine the page aligned address
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Addr pageAddress(Addr addr) const;
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//! number of prefetch streams available
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uint32_t m_num_streams;
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//! an array of the active prefetch streams
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std::vector<PrefetchEntry> m_array;
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//! number of misses I must see before allocating a stream
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uint32_t m_train_misses;
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//! number of initial prefetches to startup a stream
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uint32_t m_num_startup_pfs;
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/**
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* A unit stride filter array: helps reduce BW requirement
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* of prefetching.
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*/
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CircularQueue<UnitFilterEntry> unitFilter;
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/**
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* A negative unit stride filter array: helps reduce BW requirement
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* of prefetching.
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*/
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CircularQueue<UnitFilterEntry> negativeFilter;
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/**
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* A non-unit stride filter array: helps reduce BW requirement of
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* prefetching.
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*/
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CircularQueue<NonUnitFilterEntry> nonUnitFilter;
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/// Used for allowing prefetches across pages.
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bool m_prefetch_cross_pages;
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AbstractController *m_controller;
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const unsigned pageShift;
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int m_block_size_bits = 0;
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int m_block_size_bytes = 0;
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Addr
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makeNextStrideAddress(Addr addr, int stride) const
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{
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return ruby::makeNextStrideAddress(addr, stride,
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m_block_size_bytes);
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}
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struct RubyPrefetcherStats : public statistics::Group
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{
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RubyPrefetcherStats(statistics::Group *parent);
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//! Count of accesses to the prefetcher
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statistics::Scalar numMissObserved;
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//! Count of prefetch streams allocated
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statistics::Scalar numAllocatedStreams;
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//! Count of prefetch requests made
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statistics::Scalar numPrefetchRequested;
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//! Count of successful prefetches
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statistics::Scalar numHits;
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//! Count of partial successful prefetches
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statistics::Scalar numPartialHits;
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//! Count of pages crossed
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statistics::Scalar numPagesCrossed;
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//! Count of misses incurred for blocks that were prefetched
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statistics::Scalar numMissedPrefetchedBlocks;
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} rubyPrefetcherStats;
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};
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} // namespace ruby
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} // namespace gem5
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#endif // __MEM_RUBY_STRUCTURES_PREFETCHER_HH__
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