974a47dfb9
Apply the gem5 namespace to the codebase. Some anonymous namespaces could theoretically be removed, but since this change's main goal was to keep conflicts at a minimum, it was decided not to modify much the general shape of the files. A few missing comments of the form "// namespace X" that occurred before the newly added "} // namespace gem5" have been added for consistency. std out should not be included in the gem5 namespace, so they weren't. ProtoMessage has not been included in the gem5 namespace, since I'm not familiar with how proto works. Regarding the SystemC files, although they belong to gem5, they actually perform integration between gem5 and SystemC; therefore, it deserved its own separate namespace. Files that are automatically generated have been included in the gem5 namespace. The .isa files currently are limited to a single namespace. This limitation should be later removed to make it easier to accomodate a better API. Regarding the files in util, gem5:: was prepended where suitable. Notice that this patch was tested as much as possible given that most of these were already not previously compiling. Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
108 lines
5.2 KiB
Python
108 lines
5.2 KiB
Python
# Copyright (c) 2012-2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2013 Amin Farmahini-Farahani
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# Copyright (c) 2015 University of Kaiserslautern
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# Copyright (c) 2015 The University of Bologna
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.proxy import *
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from m5.objects.AbstractMemory import AbstractMemory
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# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
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# channel, rank, bank, row and column, respectively, and going from
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# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
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# suitable for an open-page policy, optimising for sequential accesses
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# hitting in the open row. For a closed-page policy, RoCoRaBaCh
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# maximises parallelism.
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class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
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class MemInterface(AbstractMemory):
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type = 'MemInterface'
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abstract = True
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cxx_header = "mem/mem_interface.hh"
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cxx_class = 'gem5::MemInterface'
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# Allow the interface to set required controller buffer sizes
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# each entry corresponds to a burst for the specific memory channel
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# configuration (e.g. x32 with burst length 8 is 32 bytes) and not
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# the cacheline size or request/packet size
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write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
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read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
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# scheduler, address map
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addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
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# size of memory device in Bytes
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device_size = Param.MemorySize("Size of memory device")
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# the physical organisation of the memory
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device_bus_width = Param.Unsigned("data bus width in bits for each "\
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"memory device/chip")
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burst_length = Param.Unsigned("Burst lenght (BL) in beats")
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device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
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"device/chip")
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devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
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ranks_per_channel = Param.Unsigned("Number of ranks per channel")
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banks_per_rank = Param.Unsigned("Number of banks per rank")
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# timing behaviour and constraints - all in nanoseconds
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# the base clock period of the memory
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tCK = Param.Latency("Clock period")
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# time to complete a burst transfer, typically the burst length
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# divided by two due to the DDR bus, but by making it a parameter
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# it is easier to also evaluate SDR memories like WideIO and new
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# interfaces, emerging technologies.
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# This parameter has to account for burst length.
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# Read/Write requests with data size larger than one full burst are broken
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# down into multiple requests in the controller
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tBURST = Param.Latency("Burst duration "
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"(typically burst length / 2 cycles)")
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# write-to-read, same rank turnaround penalty
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tWTR = Param.Latency("Write to read, same rank switching time")
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# read-to-write, same rank turnaround penalty
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tRTW = Param.Latency("Read to write, same rank switching time")
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# rank-to-rank bus delay penalty
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# this does not correlate to a memory timing parameter and encompasses:
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# 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
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# different rank bus delay
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tCS = Param.Latency("Rank to rank switching time")
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