974a47dfb9
Apply the gem5 namespace to the codebase. Some anonymous namespaces could theoretically be removed, but since this change's main goal was to keep conflicts at a minimum, it was decided not to modify much the general shape of the files. A few missing comments of the form "// namespace X" that occurred before the newly added "} // namespace gem5" have been added for consistency. std out should not be included in the gem5 namespace, so they weren't. ProtoMessage has not been included in the gem5 namespace, since I'm not familiar with how proto works. Regarding the SystemC files, although they belong to gem5, they actually perform integration between gem5 and SystemC; therefore, it deserved its own separate namespace. Files that are automatically generated have been included in the gem5 namespace. The .isa files currently are limited to a single namespace. This limitation should be later removed to make it easier to accomodate a better API. Regarding the files in util, gem5:: was prepended where suitable. Notice that this patch was tested as much as possible given that most of these were already not previously compiling. Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
283 lines
11 KiB
Python
283 lines
11 KiB
Python
# Copyright (c) 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.defines import buildEnv
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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from m5.objects.PciDevice import PciDevice, PciIoBar, PciMemBar
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ETHERNET_ROLE = 'ETHERNET'
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Port.compat(ETHERNET_ROLE, ETHERNET_ROLE)
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class EtherInt(Port):
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def __init__(self, desc):
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super(EtherInt, self).__init__(ETHERNET_ROLE, desc)
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class VectorEtherInt(VectorPort):
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def __init__(self, desc):
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super(VectorEtherInt, self).__init__(ETHERNET_ROLE, desc)
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class EtherLink(SimObject):
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type = 'EtherLink'
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cxx_header = "dev/net/etherlink.hh"
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cxx_class = 'gem5::EtherLink'
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int0 = EtherInt("interface 0")
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int1 = EtherInt("interface 1")
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delay = Param.Latency('0us', "packet transmit delay")
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delay_var = Param.Latency('0ns', "packet transmit delay variability")
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speed = Param.NetworkBandwidth('1Gbps', "link speed")
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dump = Param.EtherDump(NULL, "dump object")
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class DistEtherLink(SimObject):
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type = 'DistEtherLink'
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cxx_header = "dev/net/dist_etherlink.hh"
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cxx_class = 'gem5::DistEtherLink'
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int0 = EtherInt("interface 0")
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delay = Param.Latency('0us', "packet transmit delay")
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delay_var = Param.Latency('0ns', "packet transmit delay variability")
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speed = Param.NetworkBandwidth('1Gbps', "link speed")
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dump = Param.EtherDump(NULL, "dump object")
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dist_rank = Param.UInt32('0', "Rank of this gem5 process (dist run)")
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dist_size = Param.UInt32('1', "Number of gem5 processes (dist run)")
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sync_start = Param.Latency('5200000000000t', "first dist sync barrier")
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sync_repeat = Param.Latency('10us', "dist sync barrier repeat")
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server_name = Param.String('localhost', "Message server name")
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server_port = Param.UInt32('2200', "Message server port")
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is_switch = Param.Bool(False, "true if this a link in etherswitch")
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dist_sync_on_pseudo_op = Param.Bool(False, "Start sync with pseudo_op")
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num_nodes = Param.UInt32('2', "Number of simulate nodes")
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class EtherBus(SimObject):
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type = 'EtherBus'
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cxx_header = "dev/net/etherbus.hh"
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cxx_class = 'gem5::EtherBus'
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loopback = Param.Bool(True, "send packet back to the sending interface")
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dump = Param.EtherDump(NULL, "dump object")
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speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
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class EtherSwitch(SimObject):
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type = 'EtherSwitch'
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cxx_header = "dev/net/etherswitch.hh"
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cxx_class = 'gem5::EtherSwitch'
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dump = Param.EtherDump(NULL, "dump object")
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fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed in "
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"bits per second")
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interface = VectorEtherInt("Ethernet Interface")
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output_buffer_size = Param.MemorySize('1MiB',
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"size of output port buffers")
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delay = Param.Latency('0us', "packet transmit delay")
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delay_var = Param.Latency('0ns', "packet transmit delay variability")
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time_to_live = Param.Latency('10ms', "time to live of MAC address maping")
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class EtherTapBase(SimObject):
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type = 'EtherTapBase'
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abstract = True
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cxx_header = "dev/net/ethertap.hh"
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cxx_class = 'gem5::EtherTapBase'
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bufsz = Param.Int(10000, "tap buffer size")
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dump = Param.EtherDump(NULL, "dump object")
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tap = EtherInt("Ethernet interface to connect to gem5's network")
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if buildEnv['HAVE_TUNTAP']:
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class EtherTap(EtherTapBase):
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type = 'EtherTap'
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cxx_header = "dev/net/ethertap.hh"
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cxx_class = 'gem5::EtherTap'
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tun_clone_device = Param.String('/dev/net/tun',
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"Path to the tun clone device node")
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tap_device_name = Param.String('gem5-tap', "Tap device name")
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class EtherTapStub(EtherTapBase):
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type = 'EtherTapStub'
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cxx_header = "dev/net/ethertap.hh"
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cxx_class = 'gem5::EtherTapStub'
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port = Param.UInt16(3500, "Port helper should send packets to")
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class EtherDump(SimObject):
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type = 'EtherDump'
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cxx_header = "dev/net/etherdump.hh"
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cxx_class = 'gem5::EtherDump'
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file = Param.String("dump file")
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maxlen = Param.Int(96, "max portion of packet data to dump")
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class EtherDevice(PciDevice):
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type = 'EtherDevice'
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abstract = True
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cxx_header = "dev/net/etherdevice.hh"
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cxx_class = 'gem5::EtherDevice'
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interface = EtherInt("Ethernet Interface")
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class IGbE(EtherDevice):
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# Base class for two IGbE adapters listed above
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type = 'IGbE'
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cxx_header = "dev/net/i8254xGBe.hh"
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cxx_class = 'gem5::IGbE'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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rx_fifo_size = Param.MemorySize('384KiB', "Size of the rx FIFO")
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tx_fifo_size = Param.MemorySize('384KiB', "Size of the tx FIFO")
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rx_desc_cache_size = Param.Int(64,
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"Number of enteries in the rx descriptor cache")
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tx_desc_cache_size = Param.Int(64,
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"Number of enteries in the rx descriptor cache")
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VendorID = 0x8086
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SubsystemID = 0x1008
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SubsystemVendorID = 0x8086
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Status = 0x0000
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = PciMemBar(size='128KiB')
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MaximumLatency = 0x00
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MinimumGrant = 0xff
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InterruptLine = 0x1e
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InterruptPin = 0x01
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wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
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fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
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fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
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wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
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tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
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rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
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phy_pid = Param.UInt16("Phy PID that corresponds to device ID")
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phy_epid = Param.UInt16("Phy EPID that corresponds to device ID")
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class IGbE_e1000(IGbE):
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# Older Intel 8254x based gigabit ethernet adapter
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# Uses Intel e1000 driver
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DeviceID = 0x1075
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phy_pid = 0x02A8
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phy_epid = 0x0380
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class IGbE_igb(IGbE):
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# Newer Intel 8257x based gigabit ethernet adapter
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# Uses Intel igb driver and in theory supports packet splitting and LRO
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DeviceID = 0x10C9
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phy_pid = 0x0141
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phy_epid = 0x0CC0
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class EtherDevBase(EtherDevice):
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type = 'EtherDevBase'
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abstract = True
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cxx_header = "dev/net/etherdevice.hh"
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cxx_class = 'gem5::EtherDevBase'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
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dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
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dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
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dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
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rx_delay = Param.Latency('1us', "Receive Delay")
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tx_delay = Param.Latency('1us', "Transmit Delay")
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rx_fifo_size = Param.MemorySize('512KiB', "max size of rx fifo")
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tx_fifo_size = Param.MemorySize('512KiB', "max size of tx fifo")
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rx_filter = Param.Bool(True, "Enable Receive Filter")
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intr_delay = Param.Latency('10us', "Interrupt propagation delay")
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rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
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tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
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rss = Param.Bool(False, "Receive Side Scaling")
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class NSGigE(EtherDevBase):
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type = 'NSGigE'
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cxx_header = "dev/net/ns_gige.hh"
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cxx_class = 'gem5::NSGigE'
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dma_data_free = Param.Bool(False, "DMA of Data is free")
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dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
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dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
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VendorID = 0x100B
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DeviceID = 0x0022
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BARs = (PciIoBar(size='256B'), PciMemBar(size='4KiB'))
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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class Sinic(EtherDevBase):
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type = 'Sinic'
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cxx_class = 'gem5::sinic::Device'
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cxx_header = "dev/net/sinic.hh"
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rx_max_copy = Param.MemorySize('1514B', "rx max copy")
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tx_max_copy = Param.MemorySize('16KiB', "tx max copy")
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rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
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rx_fifo_threshold = Param.MemorySize('384KiB', "rx fifo high threshold")
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rx_fifo_low_mark = Param.MemorySize('128KiB', "rx fifo low threshold")
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tx_fifo_high_mark = Param.MemorySize('384KiB', "tx fifo high threshold")
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tx_fifo_threshold = Param.MemorySize('128KiB', "tx fifo low threshold")
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virtual_count = Param.UInt32(1, "Virtualized SINIC")
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zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
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zero_copy_threshold = Param.UInt32(256,
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"Only zero copy above this threshold")
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zero_copy = Param.Bool(False, "Zero copy receive")
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delay_copy = Param.Bool(False, "Delayed copy transmit")
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virtual_addr = Param.Bool(False, "Virtual addressing")
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VendorID = 0x1291
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DeviceID = 0x1293
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BARs = PciMemBar(size='64KiB')
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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