Apply the gem5 namespace to the codebase. Some anonymous namespaces could theoretically be removed, but since this change's main goal was to keep conflicts at a minimum, it was decided not to modify much the general shape of the files. A few missing comments of the form "// namespace X" that occurred before the newly added "} // namespace gem5" have been added for consistency. std out should not be included in the gem5 namespace, so they weren't. ProtoMessage has not been included in the gem5 namespace, since I'm not familiar with how proto works. Regarding the SystemC files, although they belong to gem5, they actually perform integration between gem5 and SystemC; therefore, it deserved its own separate namespace. Files that are automatically generated have been included in the gem5 namespace. The .isa files currently are limited to a single namespace. This limitation should be later removed to make it easier to accomodate a better API. Regarding the files in util, gem5:: was prepended where suitable. Notice that this patch was tested as much as possible given that most of these were already not previously compiling. Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
365 lines
12 KiB
C++
365 lines
12 KiB
C++
/*
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* Copyright (c) 2017-2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/testers/gpu_ruby_test/protocol_tester.hh"
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#include <algorithm>
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#include <ctime>
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#include <fstream>
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#include <random>
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#include "cpu/testers/gpu_ruby_test/cpu_thread.hh"
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#include "cpu/testers/gpu_ruby_test/dma_thread.hh"
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#include "cpu/testers/gpu_ruby_test/gpu_wavefront.hh"
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#include "cpu/testers/gpu_ruby_test/tester_thread.hh"
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#include "debug/ProtocolTest.hh"
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#include "mem/request.hh"
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#include "sim/sim_exit.hh"
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#include "sim/system.hh"
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namespace gem5
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{
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ProtocolTester::ProtocolTester(const Params &p)
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: ClockedObject(p),
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_requestorId(p.system->getRequestorId(this)),
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numCpuPorts(p.port_cpu_ports_connection_count),
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numDmaPorts(p.port_dma_ports_connection_count),
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numVectorPorts(p.port_cu_vector_ports_connection_count),
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numSqcPorts(p.port_cu_sqc_ports_connection_count),
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numScalarPorts(p.port_cu_scalar_ports_connection_count),
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numTokenPorts(p.port_cu_token_ports_connection_count),
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numCusPerSqc(p.cus_per_sqc),
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numCusPerScalar(p.cus_per_scalar),
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numWfsPerCu(p.wavefronts_per_cu),
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numWisPerWf(p.workitems_per_wavefront),
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numCuTokens(p.max_cu_tokens),
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numAtomicLocs(p.num_atomic_locations),
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numNormalLocsPerAtomic(p.num_normal_locs_per_atomic),
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episodeLength(p.episode_length),
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maxNumEpisodes(p.max_num_episodes),
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debugTester(p.debug_tester),
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cpuThreads(p.cpu_threads),
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dmaThreads(p.dma_threads),
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wfs(p.wavefronts)
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{
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int idx = 0; // global port index
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numCpus = numCpuPorts; // 1 cpu port per CPU
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numDmas = numDmaPorts; // 1 dma port per DMA
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numCus = numVectorPorts; // 1 vector port per CU
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// create all physical cpu's data ports
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for (int i = 0; i < numCpuPorts; ++i) {
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DPRINTF(ProtocolTest, "Creating %s\n",
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csprintf("%s-cpuPort%d", name(), i));
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cpuPorts.push_back(new SeqPort(csprintf("%s-cpuPort%d", name(), i),
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this, i, idx));
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idx++;
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}
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// create all physical DMA data ports
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for (int i = 0; i < numDmaPorts; ++i) {
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DPRINTF(ProtocolTest, "Creating %s\n",
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csprintf("%s-dmaPort%d", name(), i));
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dmaPorts.push_back(new SeqPort(csprintf("%s-dmaPort%d", name(), i),
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this, i, idx));
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idx++;
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}
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// create all physical gpu's data ports
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for (int i = 0; i < numVectorPorts; ++i) {
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DPRINTF(ProtocolTest, "Creating %s\n",
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csprintf("%s-cuVectorPort%d", name(), i));
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cuVectorPorts.push_back(new SeqPort(csprintf("%s-cuVectorPort%d",
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name(), i),
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this, i, idx));
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idx++;
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}
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for (int i = 0; i < numScalarPorts; ++i) {
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DPRINTF(ProtocolTest, "Creating %s\n",
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csprintf("%s-cuScalarPort%d", name(), i));
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cuScalarPorts.push_back(new SeqPort(csprintf("%s-cuScalarPort%d",
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name(), i),
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this, i, idx));
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idx++;
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}
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for (int i = 0; i < numSqcPorts; ++i) {
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DPRINTF(ProtocolTest, "Creating %s\n",
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csprintf("%s-cuSqcPort%d", name(), i));
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cuSqcPorts.push_back(new SeqPort(csprintf("%s-cuSqcPort%d",
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name(), i),
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this, i, idx));
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idx++;
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}
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for (int i = 0; i < numTokenPorts; ++i) {
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cuTokenPorts.push_back(new GMTokenPort(csprintf("%s-cuTokenPort%d",
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name(), i),
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this, i));
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cuTokenManagers.push_back(new TokenManager(numCuTokens));
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cuTokenPorts[i]->setTokenManager(cuTokenManagers[i]);
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}
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// create an address manager
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addrManager = new AddressManager(numAtomicLocs,
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numNormalLocsPerAtomic);
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nextEpisodeId = 0;
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if (!debugTester)
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warn("Data race check is not enabled\n");
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sentExitSignal = false;
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// set random seed number
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if (p.random_seed != 0) {
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srand(p.random_seed);
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} else {
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srand(time(NULL));
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}
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actionCount = 0;
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// create a new log file
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logFile = simout.create(p.log_file);
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assert(logFile);
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// print test configs
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std::stringstream ss;
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ss << "GPU Ruby test's configurations" << std::endl
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<< "\tNumber of CPUs: " << numCpus << std::endl
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<< "\tNumber of DMAs: " << numDmas << std::endl
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<< "\tNumber of CUs: " << numCus << std::endl
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<< "\tNumber of wavefronts per CU: " << numWfsPerCu << std::endl
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<< "\tWavefront size: " << numWisPerWf << std::endl
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<< "\tNumber of atomic locations: " << numAtomicLocs << std::endl
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<< "\tNumber of non-atomic locations: "
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<< numNormalLocsPerAtomic * numAtomicLocs << std::endl
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<< "\tEpisode length: " << episodeLength << std::endl
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<< "\tTest length (max number of episodes): " << maxNumEpisodes
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<< std::endl
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<< "\tRandom seed: " << p.random_seed
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<< std::endl;
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ccprintf(*(logFile->stream()), "%s", ss.str());
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logFile->stream()->flush();
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}
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ProtocolTester::~ProtocolTester()
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{
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for (int i = 0; i < cpuPorts.size(); ++i)
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delete cpuPorts[i];
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for (int i = 0; i < dmaPorts.size(); ++i)
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delete dmaPorts[i];
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for (int i = 0; i < cuVectorPorts.size(); ++i)
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delete cuVectorPorts[i];
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for (int i = 0; i < cuScalarPorts.size(); ++i)
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delete cuScalarPorts[i];
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for (int i = 0; i < cuSqcPorts.size(); ++i)
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delete cuSqcPorts[i];
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delete addrManager;
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// close the log file
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simout.close(logFile);
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}
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void
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ProtocolTester::init()
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{
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DPRINTF(ProtocolTest, "Attach threads to ports\n");
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// connect cpu threads to cpu's ports
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for (int cpu_id = 0; cpu_id < numCpus; ++cpu_id) {
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cpuThreads[cpu_id]->attachTesterThreadToPorts(this,
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static_cast<SeqPort*>(cpuPorts[cpu_id]));
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cpuThreads[cpu_id]->scheduleWakeup();
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cpuThreads[cpu_id]->scheduleDeadlockCheckEvent();
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}
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// connect dma threads to dma's ports
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for (int dma_id = 0; dma_id < numDmas; ++dma_id) {
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dmaThreads[dma_id]->attachTesterThreadToPorts(this,
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static_cast<SeqPort*>(dmaPorts[dma_id]));
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dmaThreads[dma_id]->scheduleWakeup();
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dmaThreads[dma_id]->scheduleDeadlockCheckEvent();
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}
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// connect gpu wavefronts to gpu's ports
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int wfId = 0;
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int vectorPortId = 0;
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int sqcPortId = 0;
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int scalarPortId = 0;
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for (int cu_id = 0; cu_id < numCus; ++cu_id) {
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vectorPortId = cu_id;
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sqcPortId = cu_id/numCusPerSqc;
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scalarPortId = cu_id/numCusPerScalar;
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for (int i = 0; i < numWfsPerCu; ++i) {
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wfId = cu_id * numWfsPerCu + i;
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wfs[wfId]->attachTesterThreadToPorts(this,
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static_cast<SeqPort*>(cuVectorPorts[vectorPortId]),
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cuTokenPorts[vectorPortId],
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static_cast<SeqPort*>(cuSqcPorts[sqcPortId]),
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static_cast<SeqPort*>(cuScalarPorts[scalarPortId]));
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wfs[wfId]->scheduleWakeup();
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wfs[wfId]->scheduleDeadlockCheckEvent();
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}
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}
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}
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Port&
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ProtocolTester::getPort(const std::string &if_name, PortID idx)
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{
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if (if_name != "cpu_ports" && if_name != "dma_ports" &&
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if_name != "cu_vector_ports" && if_name != "cu_sqc_ports" &&
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if_name != "cu_scalar_ports" && if_name != "cu_token_ports") {
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// pass along to super class
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return ClockedObject::getPort(if_name, idx);
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} else {
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if (if_name == "cpu_ports") {
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if (idx > numCpuPorts)
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panic("ProtocolTester: unknown cpu port %d\n", idx);
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return *cpuPorts[idx];
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} else if (if_name == "dma_ports") {
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if (idx > numDmaPorts)
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panic("ProtocolTester: unknown dma port %d\n", idx);
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return *dmaPorts[idx];
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} else if (if_name == "cu_vector_ports") {
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if (idx > numVectorPorts)
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panic("ProtocolTester: unknown cu vect port %d\n", idx);
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return *cuVectorPorts[idx];
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} else if (if_name == "cu_sqc_ports") {
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if (idx > numSqcPorts)
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panic("ProtocolTester: unknown cu sqc port %d\n", idx);
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return *cuSqcPorts[idx];
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} else if (if_name == "cu_token_ports") {
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if (idx > numTokenPorts)
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panic("ProtocolTester: unknown cu token port %d\n", idx);
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return *cuTokenPorts[idx];
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} else {
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assert(if_name == "cu_scalar_ports");
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if (idx > numScalarPorts)
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panic("ProtocolTester: unknown cu scal port %d\n", idx);
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return *cuScalarPorts[idx];
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}
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}
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assert(false);
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}
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bool
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ProtocolTester::checkExit()
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{
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if (nextEpisodeId > maxNumEpisodes) {
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if (!sentExitSignal) {
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// all done
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inform("Total completed episodes: %d\n", nextEpisodeId - 1);
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exitSimLoop("GPU Ruby Tester: Passed!");
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sentExitSignal = true;
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}
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return true;
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}
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return false;
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}
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bool
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ProtocolTester::checkDRF(Location atomic_loc,
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Location loc, bool isStore) const
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{
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if (debugTester) {
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// go through all active episodes in all threads
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for (const TesterThread* th : wfs) {
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if (!th->checkDRF(atomic_loc, loc, isStore))
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return false;
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}
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for (const TesterThread* th : cpuThreads) {
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if (!th->checkDRF(atomic_loc, loc, isStore))
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return false;
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}
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for (const TesterThread* th : dmaThreads) {
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if (!th->checkDRF(atomic_loc, loc, isStore))
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return false;
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}
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}
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return true;
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}
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void
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ProtocolTester::dumpErrorLog(std::stringstream& ss)
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{
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if (!sentExitSignal) {
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// go through all threads and dump their outstanding requests
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for (auto t : cpuThreads) {
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t->printAllOutstandingReqs(ss);
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}
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for (auto t : dmaThreads) {
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t->printAllOutstandingReqs(ss);
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}
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for (auto t : wfs) {
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t->printAllOutstandingReqs(ss);
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}
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// dump error log into a file
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assert(logFile);
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ccprintf(*(logFile->stream()), "%s", ss.str());
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logFile->stream()->flush();
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sentExitSignal = true;
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// terminate the simulation
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panic("GPU Ruby Tester: Failed!\n");
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}
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}
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bool
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ProtocolTester::SeqPort::recvTimingResp(PacketPtr pkt)
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{
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// get the requesting thread from the original sender state
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ProtocolTester::SenderState* senderState =
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safe_cast<ProtocolTester::SenderState*>(pkt->senderState);
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TesterThread *th = senderState->th;
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th->hitCallback(pkt);
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return true;
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}
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} // namespace gem5
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