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972c38b1cc5f6f6c649a0e9923695447bc5d6255
gem5/src/cpu/pred
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Gabe Black 972c38b1cc arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code. 
This code will be preserved through version control, but otherwise
creates clutter and will rot in place since it's never compiled.

Change-Id: Id265f6deac445116843956ea5cf1210d8127274e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-18 10:20:20 +00:00
..
2bit_local.cc
arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.
2019-05-18 10:20:20 +00:00
2bit_local.hh
base: Move SatCounter to base directory
2019-05-14 07:55:06 +00:00
bi_mode.cc
cpu: Revamp saturating counters
2019-05-14 07:55:06 +00:00
bi_mode.hh
base: Move SatCounter to base directory
2019-05-14 07:55:06 +00:00
bpred_unit.cc
cpu: Make the indirect predictor into a SimObject
2019-05-13 11:43:50 +00:00
bpred_unit.hh
cpu: Make the indirect predictor into a SimObject
2019-05-13 11:43:50 +00:00
BranchPredictor.py
cpu: Make the indirect predictor into a SimObject
2019-05-13 11:43:50 +00:00
btb.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
btb.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
indirect.cc
cpu: Make the indirect predictor into a SimObject
2019-05-13 11:43:50 +00:00
indirect.hh
cpu: Make the indirect predictor into a SimObject
2019-05-13 11:43:50 +00:00
loop_predictor.cc
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
loop_predictor.hh
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
ltage.cc
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
ltage.hh
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
ras.cc
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
2010-10-31 00:07:20 -07:00
ras.hh
branch predictor: move out of o3 and inorder cpus
2013-01-24 12:28:51 -06:00
SConscript
cpu: Make the indirect predictor into a SimObject
2019-05-13 11:43:50 +00:00
simple_indirect.cc
cpu: Make the indirect predictor into a SimObject
2019-05-13 11:43:50 +00:00
simple_indirect.hh
cpu: Make the indirect predictor into a SimObject
2019-05-13 11:43:50 +00:00
statistical_corrector.cc
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
statistical_corrector.hh
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
tage_base.cc
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
tage_base.hh
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
tage_sc_l_8KB.cc
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
tage_sc_l_8KB.hh
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
tage_sc_l_64KB.cc
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
tage_sc_l_64KB.hh
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
tage_sc_l.cc
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
tage_sc_l.hh
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
tage.cc
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
tage.hh
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-13 21:34:15 +00:00
tournament.cc
cpu: Revamp saturating counters
2019-05-14 07:55:06 +00:00
tournament.hh
base: Move SatCounter to base directory
2019-05-14 07:55:06 +00:00