96c999fe88
Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to print statements. So the addresses which were being printed in hex earlier along with their line address, were now being printed in decimals. This patch adds a function printAddress(Addr) that can be used to print the address in hex along with the lines address. This function has been put to use in some of the places. At other places, change has been made to print just the address in hex.
350 lines
11 KiB
C++
350 lines
11 KiB
C++
/*
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* Copyright (c) 2011-2014 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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#include "debug/RubyQueue.hh"
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#include "mem/protocol/MemoryMsg.hh"
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#include "mem/ruby/system/RubySystem.hh"
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#include "mem/ruby/system/Sequencer.hh"
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#include "sim/system.hh"
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AbstractController::AbstractController(const Params *p)
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: MemObject(p), Consumer(this), m_version(p->version),
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m_clusterID(p->cluster_id),
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m_masterId(p->system->getMasterId(name())), m_is_blocking(false),
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m_number_of_TBEs(p->number_of_TBEs),
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m_transitions_per_cycle(p->transitions_per_cycle),
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m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency),
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memoryPort(csprintf("%s.memory", name()), this, "")
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{
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if (m_version == 0) {
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// Combine the statistics from all controllers
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// of this particular type.
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Stats::registerDumpCallback(new StatsCallback(this));
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}
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}
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void
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AbstractController::init()
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{
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params()->ruby_system->registerAbstractController(this);
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m_delayHistogram.init(10);
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uint32_t size = Network::getNumberOfVirtualNetworks();
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for (uint32_t i = 0; i < size; i++) {
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m_delayVCHistogram.push_back(new Stats::Histogram());
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m_delayVCHistogram[i]->init(10);
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}
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}
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void
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AbstractController::resetStats()
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{
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m_delayHistogram.reset();
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uint32_t size = Network::getNumberOfVirtualNetworks();
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for (uint32_t i = 0; i < size; i++) {
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m_delayVCHistogram[i]->reset();
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}
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}
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void
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AbstractController::regStats()
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{
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m_fully_busy_cycles
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.name(name() + ".fully_busy_cycles")
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.desc("cycles for which number of transistions == max transitions")
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.flags(Stats::nozero);
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}
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void
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AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
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{
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assert(virtualNetwork < m_delayVCHistogram.size());
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m_delayHistogram.sample(delay);
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m_delayVCHistogram[virtualNetwork]->sample(delay);
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}
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void
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AbstractController::stallBuffer(MessageBuffer* buf, Addr addr)
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{
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if (m_waiting_buffers.count(addr) == 0) {
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MsgVecType* msgVec = new MsgVecType;
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msgVec->resize(m_in_ports, NULL);
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m_waiting_buffers[addr] = msgVec;
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}
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DPRINTF(RubyQueue, "stalling %s port %d addr %#x\n", buf, m_cur_in_port,
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addr);
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assert(m_in_ports > m_cur_in_port);
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(*(m_waiting_buffers[addr]))[m_cur_in_port] = buf;
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}
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void
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AbstractController::wakeUpBuffers(Addr addr)
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{
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if (m_waiting_buffers.count(addr) > 0) {
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//
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// Wake up all possible lower rank (i.e. lower priority) buffers that could
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// be waiting on this message.
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//
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for (int in_port_rank = m_cur_in_port - 1;
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in_port_rank >= 0;
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in_port_rank--) {
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if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
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(*(m_waiting_buffers[addr]))[in_port_rank]->
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reanalyzeMessages(addr, clockEdge());
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}
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}
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delete m_waiting_buffers[addr];
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m_waiting_buffers.erase(addr);
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}
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}
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void
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AbstractController::wakeUpAllBuffers(Addr addr)
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{
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if (m_waiting_buffers.count(addr) > 0) {
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//
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// Wake up all possible lower rank (i.e. lower priority) buffers that could
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// be waiting on this message.
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//
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for (int in_port_rank = m_in_ports - 1;
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in_port_rank >= 0;
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in_port_rank--) {
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if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
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(*(m_waiting_buffers[addr]))[in_port_rank]->
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reanalyzeMessages(addr, clockEdge());
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}
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}
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delete m_waiting_buffers[addr];
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m_waiting_buffers.erase(addr);
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}
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}
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void
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AbstractController::wakeUpAllBuffers()
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{
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//
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// Wake up all possible buffers that could be waiting on any message.
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//
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std::vector<MsgVecType*> wokeUpMsgVecs;
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MsgBufType wokeUpMsgBufs;
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if(m_waiting_buffers.size() > 0) {
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for (WaitingBufType::iterator buf_iter = m_waiting_buffers.begin();
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buf_iter != m_waiting_buffers.end();
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++buf_iter) {
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for (MsgVecType::iterator vec_iter = buf_iter->second->begin();
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vec_iter != buf_iter->second->end();
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++vec_iter) {
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//
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// Make sure the MessageBuffer has not already be reanalyzed
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//
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if (*vec_iter != NULL &&
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(wokeUpMsgBufs.count(*vec_iter) == 0)) {
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(*vec_iter)->reanalyzeAllMessages(clockEdge());
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wokeUpMsgBufs.insert(*vec_iter);
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}
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}
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wokeUpMsgVecs.push_back(buf_iter->second);
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}
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for (std::vector<MsgVecType*>::iterator wb_iter = wokeUpMsgVecs.begin();
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wb_iter != wokeUpMsgVecs.end();
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++wb_iter) {
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delete (*wb_iter);
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}
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m_waiting_buffers.clear();
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}
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}
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void
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AbstractController::blockOnQueue(Addr addr, MessageBuffer* port)
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{
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m_is_blocking = true;
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m_block_map[addr] = port;
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}
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void
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AbstractController::unblock(Addr addr)
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{
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m_block_map.erase(addr);
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if (m_block_map.size() == 0) {
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m_is_blocking = false;
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}
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}
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BaseMasterPort &
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AbstractController::getMasterPort(const std::string &if_name,
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PortID idx)
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{
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return memoryPort;
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}
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void
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AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
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Cycles latency)
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{
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RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
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m_masterId);
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PacketPtr pkt = Packet::createRead(req);
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uint8_t *newData = new uint8_t[RubySystem::getBlockSizeBytes()];
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pkt->dataDynamic(newData);
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SenderState *s = new SenderState(id);
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pkt->pushSenderState(s);
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// Use functional rather than timing accesses during warmup
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if (RubySystem::getWarmupEnabled()) {
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memoryPort.sendFunctional(pkt);
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recvTimingResp(pkt);
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return;
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}
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memoryPort.schedTimingReq(pkt, clockEdge(latency));
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}
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void
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AbstractController::queueMemoryWrite(const MachineID &id, Addr addr,
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Cycles latency, const DataBlock &block)
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{
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RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
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m_masterId);
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PacketPtr pkt = Packet::createWrite(req);
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uint8_t *newData = new uint8_t[RubySystem::getBlockSizeBytes()];
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pkt->dataDynamic(newData);
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memcpy(newData, block.getData(0, RubySystem::getBlockSizeBytes()),
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RubySystem::getBlockSizeBytes());
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SenderState *s = new SenderState(id);
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pkt->pushSenderState(s);
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// Use functional rather than timing accesses during warmup
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if (RubySystem::getWarmupEnabled()) {
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memoryPort.sendFunctional(pkt);
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recvTimingResp(pkt);
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return;
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}
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// Create a block and copy data from the block.
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memoryPort.schedTimingReq(pkt, clockEdge(latency));
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}
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void
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AbstractController::queueMemoryWritePartial(const MachineID &id, Addr addr,
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Cycles latency,
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const DataBlock &block, int size)
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{
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RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
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m_masterId);
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PacketPtr pkt = Packet::createWrite(req);
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uint8_t *newData = new uint8_t[size];
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pkt->dataDynamic(newData);
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memcpy(newData, block.getData(getOffset(addr), size), size);
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SenderState *s = new SenderState(id);
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pkt->pushSenderState(s);
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// Create a block and copy data from the block.
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memoryPort.schedTimingReq(pkt, clockEdge(latency));
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}
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void
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AbstractController::functionalMemoryRead(PacketPtr pkt)
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{
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memoryPort.sendFunctional(pkt);
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}
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int
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AbstractController::functionalMemoryWrite(PacketPtr pkt)
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{
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int num_functional_writes = 0;
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// Check the buffer from the controller to the memory.
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if (memoryPort.checkFunctional(pkt)) {
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num_functional_writes++;
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}
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// Update memory itself.
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memoryPort.sendFunctional(pkt);
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return num_functional_writes + 1;
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}
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void
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AbstractController::recvTimingResp(PacketPtr pkt)
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{
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assert(getMemoryQueue());
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assert(pkt->isResponse());
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std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge());
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(*msg).m_addr = pkt->getAddr();
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(*msg).m_Sender = m_machineID;
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SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);
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(*msg).m_OriginalRequestorMachId = s->id;
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delete s;
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if (pkt->isRead()) {
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(*msg).m_Type = MemoryRequestType_MEMORY_READ;
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(*msg).m_MessageSize = MessageSizeType_Response_Data;
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// Copy data from the packet
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(*msg).m_DataBlk.setData(pkt->getPtr<uint8_t>(), 0,
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RubySystem::getBlockSizeBytes());
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} else if (pkt->isWrite()) {
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(*msg).m_Type = MemoryRequestType_MEMORY_WB;
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(*msg).m_MessageSize = MessageSizeType_Writeback_Control;
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} else {
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panic("Incorrect packet type received from memory controller!");
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}
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getMemoryQueue()->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
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delete pkt;
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}
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bool
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AbstractController::MemoryPort::recvTimingResp(PacketPtr pkt)
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{
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controller->recvTimingResp(pkt);
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return true;
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}
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AbstractController::MemoryPort::MemoryPort(const std::string &_name,
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AbstractController *_controller,
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const std::string &_label)
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: QueuedMasterPort(_name, _controller, reqQueue, snoopRespQueue),
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reqQueue(*_controller, *this, _label),
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snoopRespQueue(*_controller, *this, _label),
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controller(_controller)
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{
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}
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