92288331c2
This code will never be executed since FULL_SYSTEM is not part of the build environment (and hasn't been for many years), and on top of that, this declaration redundantly (and incompletely) tries to set up the X86PagetableWalker that the ISA already sets up. Change-Id: I40cffbd7f60c1f741b1a14d9009f80185c9ce28c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49405 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com>
76 lines
3.6 KiB
Python
76 lines
3.6 KiB
Python
# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# For use for simulation and test purposes only
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from this
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# software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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from m5.defines import buildEnv
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from m5.params import *
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from m5.proxy import *
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from m5.objects.ClockedObject import ClockedObject
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from m5.SimObject import SimObject
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class X86GPUTLB(ClockedObject):
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type = 'X86GPUTLB'
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cxx_class = 'gem5::X86ISA::GpuTLB'
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cxx_header = 'gpu-compute/gpu_tlb.hh'
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size = Param.Int(64, "TLB size (number of entries)")
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assoc = Param.Int(64, "TLB associativity")
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if buildEnv.get('FULL_SYSTEM', False):
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walker = Param.X86PagetableWalker(X86PagetableWalker(),
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"page table walker")
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hitLatency = Param.Int(2, "Latency of a TLB hit")
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missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
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missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
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maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
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cpu_side_ports = VectorResponsePort("Ports on side closer to CPU/CU")
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slave = DeprecatedParam(cpu_side_ports,
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'`slave` is now called `cpu_side_ports`')
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mem_side_ports = VectorRequestPort("Ports on side closer to memory")
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master = DeprecatedParam(mem_side_ports,
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'`master` is now called `mem_side_ports`')
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allocationPolicy = Param.Bool(True, "Allocate on an access")
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accessDistance = Param.Bool(False, "print accessDistance stats")
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class TLBCoalescer(ClockedObject):
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type = 'TLBCoalescer'
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cxx_class = 'gem5::TLBCoalescer'
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cxx_header = 'gpu-compute/tlb_coalescer.hh'
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probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
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coalescingWindow = Param.Int(1, "Permit coalescing across that many ticks")
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cpu_side_ports = VectorResponsePort("Port on side closer to CPU/CU")
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slave = DeprecatedParam(cpu_side_ports,
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'`slave` is now called `cpu_side_ports`')
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mem_side_ports = VectorRequestPort("Port on side closer to memory")
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master = DeprecatedParam(mem_side_ports,
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'`master` is now called `mem_side_ports`')
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disableCoalescing = Param.Bool(False,"Dispable Coalescing")
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