Nilay Vaish 95381f8a99 ruby: slicc: remove double trigger, continueProcessing ...

These constructs are not in use and are not being maintained by any one.
In addition, it is not known if doubleTrigger works correctly with Ruby now.

2013-08-07 14:51:18 -05:00

..

cache

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

protocol

ruby: moesi cmp directory: separate actions for external hits

2013-06-25 00:32:04 -05:00

ruby

ruby: slicc: move some code to AbstractController

2013-08-07 14:51:18 -05:00

slicc

ruby: slicc: remove double trigger, continueProcessing

2013-08-07 14:51:18 -05:00

abstract_mem.cc

mem: Adding verbose debug output in the memory system

2013-04-22 13:20:33 -04:00

abstract_mem.hh

mem: Avoid explicitly zeroing the memory backing store

2013-05-30 12:53:54 -04:00

AbstractMemory.py

mem: Avoid explicitly zeroing the memory backing store

2013-05-30 12:53:54 -04:00

addr_mapper.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

addr_mapper.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

AddrMapper.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

bridge.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

bridge.hh

mem: Tidy up the bridge with const and additional checks

2013-06-27 05:49:49 -04:00

Bridge.py

mem: Tidy up the bridge with const and additional checks

2013-06-27 05:49:49 -04:00

bus.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

bus.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

Bus.py

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

coherent_bus.cc

mem: Make returning snoop responses occupy response layer

2013-05-30 12:54:02 -04:00

coherent_bus.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

comm_monitor.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

comm_monitor.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

CommMonitor.py

mem: Add tracing support in the communication monitor

2013-01-07 13:05:37 -05:00

fs_translating_port_proxy.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

fs_translating_port_proxy.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

mem_object.cc

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

mem_object.hh

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

MemObject.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

mport.cc

MEM: Separate snoops and normal memory requests/responses

2012-04-14 05:45:07 -04:00

mport.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

noncoherent_bus.cc

mem: Make the buses multi layered

2013-05-30 12:54:01 -04:00

noncoherent_bus.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

packet_access.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

packet_queue.cc

mem: Adding verbose debug output in the memory system

2013-04-22 13:20:33 -04:00

packet_queue.hh

sim: have a curTick per eventq

2012-11-16 10:27:47 -06:00

packet.cc

mem: Adding verbose debug output in the memory system

2013-04-22 13:20:33 -04:00

packet.hh

mem: Adding verbose debug output in the memory system

2013-04-22 13:20:33 -04:00

page_table.cc

sim: Fix two bugs relating to software caching of PageTable entries.

2013-04-23 09:47:52 -04:00

page_table.hh

sim: Fix two bugs relating to software caching of PageTable entries.

2013-04-23 09:47:52 -04:00

physical.cc

mem: Avoid explicitly zeroing the memory backing store

2013-05-30 12:53:54 -04:00

physical.hh

mem: Merge ranges that are part of the conf table

2013-01-07 13:05:38 -05:00

port_proxy.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

port_proxy.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

port.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

port.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

qport.hh

sim: Move the draining interface into a separate base class

2012-11-02 11:32:01 -05:00

request.hh

kvm: Use the address finalization code in the TLB

2013-06-18 16:10:22 +02:00

SConscript

mem: Add tracing support in the communication monitor

2013-01-07 13:05:37 -05:00

se_translating_port_proxy.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

se_translating_port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

simple_dram.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

simple_dram.hh

mem: Add bytes per activate DRAM controller stat

2013-05-30 12:54:13 -04:00

simple_mem.cc

mem: Enforce strict use of busFirst- and busLastWordTime

2013-02-19 05:56:06 -05:00

simple_mem.hh

mem: fix use after free issue in memories until 4-phase work complete.

2012-11-02 11:50:16 -05:00

SimpleDRAM.py

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

SimpleMemory.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

tport.cc

mem: Replace check with panic where inhibited should not happen

2013-04-22 13:20:33 -04:00

tport.hh

Port: Hide the queue implementation in SimpleTimingPort

2012-07-09 12:35:42 -04:00