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94926a72e91bf8af1870ae439ca4a91135427269
gem5/src/mem/cache
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Steve Reinhardt 9202422d6e Get rid of unused CacheBlk << output operator.
--HG--
extra : convert_revision : d5c0aadc35edf5c9495afcd3375f1f64716ef845
2006-10-14 02:09:05 -04:00
..
coherence
Remove bus and top level parameters from cache
2006-10-12 14:21:25 -04:00
miss
Fix problems with unCacheable addresses in timing-coherence
2006-10-12 13:33:21 -04:00
prefetch
Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches.
2006-08-15 16:21:46 -04:00
tags
Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches.
2006-08-15 16:21:46 -04:00
base_cache.cc
Fix CSHR retrys
2006-10-12 15:02:56 -04:00
base_cache.hh
Remove bus and top level parameters from cache
2006-10-12 14:21:25 -04:00
cache_blk.hh
Get rid of unused CacheBlk << output operator.
2006-10-14 02:09:05 -04:00
cache_builder.cc
Fix the packet data allocation methods. Small fixes from changesets after my initial work.
2006-06-30 11:34:27 -04:00
cache_impl.hh
Remove bus and top level parameters from cache
2006-10-12 14:21:25 -04:00
cache.cc
Was having difficulty with merging the cache, reverted to an early version and will add back in the patches to make it work soon.
2006-06-28 11:02:14 -04:00
cache.hh
Fix several bugs pertaining to upgrades/mem leaks.
2006-10-10 01:32:18 -04:00
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