93f2f69657
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu> RubyMemory is now both a driver for Ruby and a port for M5. Changed makeRequest/hitCallback interface. Brought packets (superficially) into the sequencer. Modified tester infrastructure to be packet based. and Ruby can be used together through the example ruby_se.py script. SPARC parallel applications work, and the timing *seems* right from combined M5/Ruby debug traces. To run, % build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
127 lines
4.2 KiB
C++
127 lines
4.2 KiB
C++
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id$
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*
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* Description:
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*
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*/
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#ifndef DETERMINISTICDRIVER_H
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#define DETERMINISTICDRIVER_H
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#include "mem/ruby/common/Global.hh"
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#include "mem/ruby/common/Driver.hh"
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#include "mem/ruby/common/Histogram.hh"
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#include "mem/protocol/CacheRequestType.hh"
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class RubySystem;
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class SpecifiedGenerator;
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class Packet;
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class DeterministicDriver : public Driver, public Consumer {
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public:
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// Constructors
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DeterministicDriver(RubySystem* sys_ptr);
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// Destructor
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~DeterministicDriver();
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// Public Methods
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bool isStoreReady(NodeID node);
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bool isLoadReady(NodeID node);
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bool isStoreReady(NodeID node, Address addr);
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bool isLoadReady(NodeID node, Address addr);
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void loadCompleted(NodeID node, Address addr);
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void storeCompleted(NodeID node, Address addr);
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Address getNextLoadAddr(NodeID node);
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Address getNextStoreAddr(NodeID node);
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int getLoadsCompleted() { return m_loads_completed; }
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int getStoresCompleted() { return m_stores_completed; }
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void reportDone();
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void recordLoadLatency(Time time);
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void recordStoreLatency(Time time);
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void hitCallback(Packet* pkt);
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void wakeup();
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void printStats(ostream& out) const;
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void clearStats() {}
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void printConfig(ostream& out) const {}
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void print(ostream& out) const;
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private:
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// Private Methods
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void checkForDeadlock();
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Address getNextAddr(NodeID node, Vector<NodeID> addr_vector);
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bool isAddrReady(NodeID node, Vector<NodeID> addr_vector);
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bool isAddrReady(NodeID node, Vector<NodeID> addr_vector, Address addr);
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void setNextAddr(NodeID node, Address addr, Vector<NodeID>& addr_vector);
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// Private copy constructor and assignment operator
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DeterministicDriver(const DeterministicDriver& obj);
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DeterministicDriver& operator=(const DeterministicDriver& obj);
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// Data Members (m_ prefix)
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Vector<Time> m_last_progress_vector;
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Vector<SpecifiedGenerator*> m_generator_vector;
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Vector<NodeID> m_load_vector; // Processor last to load the addr
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Vector<NodeID> m_store_vector; // Processor last to store the addr
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int m_done_counter;
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int m_loads_completed;
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int m_stores_completed;
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// enforces the previous node to have a certain # of completions
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// before next node starts
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int m_numCompletionsPerNode;
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Histogram m_load_latency;
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Histogram m_store_latency;
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Time m_finish_time;
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Time m_last_issue;
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};
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// Output operator declaration
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ostream& operator<<(ostream& out, const DeterministicDriver& obj);
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// ******************* Definitions *******************
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// Output operator definition
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extern inline
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ostream& operator<<(ostream& out, const DeterministicDriver& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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#endif //DETERMINISTICDRIVER_H
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