0a8a787de3
This patch augments the MESI_Three_Level Ruby protocol with hardware transactional memory support. The HTM implementation relies on buffering of speculative memory updates. The core notifies the L0 cache controller that a new transaction has started and the controller in turn places itself in transactional state (htmTransactionalState := true). When operating in transactional state, the usual MESI protocol changes slightly. Lines loaded or stored are marked as part of a transaction's read and write set respectively. If there is an invalidation request to cache line in the read/write set, the transaction is marked as failed. Similarly, if there is a read request by another core to a speculatively written cache line, i.e. in the write set, the transaction is marked as failed. If failed, all subsequent loads and stores from the core are made benign, i.e. made into NOPS at the cache controller, and responses are marked to indicate that the transactional state has failed. When the core receives these marked responses, it generates a HtmFailureFault with the reason for the transaction failure. Servicing this fault does two things-- (a) Restores the architectural checkpoint (b) Sends an HTM abort signal to the cache controller The restoration includes all registers in the checkpoint as well as the program counter of the instruction before the transaction started. The abort signal is sent to the L0 cache controller and resets the failed transactional state. It resets the transactional read and write sets and invalidates any speculatively written cache lines. It also exits the transactional state so that the MESI protocol operates as usual. Alternatively, if the instructions within a transaction complete without triggering a HtmFailureFault, the transaction can be committed. The core is responsible for notifying the cache controller that the transaction is complete and the cache controller makes all speculative writes visible to the rest of the system and exits the transactional state. Notifting the cache controller is done through HtmCmd Requests which are a subtype of Load Requests. KUDOS: The code is based on a previous pull request by Pradip Vallathol who developed HTM and TSX support in Gem5 as part of his master’s thesis: http://reviews.gem5.org/r/2308/index.html JIRA: https://gem5.atlassian.net/browse/GEM5-587 Change-Id: Icc328df93363486e923b8bd54f4d77741d8f5650 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30319 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
128 lines
4.5 KiB
C++
128 lines
4.5 KiB
C++
/*
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* Copyright (c) 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Common base class for a machine node.
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*/
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#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
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#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
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#include <iostream>
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#include "base/logging.hh"
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#include "mem/cache/replacement_policies/replaceable_entry.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/protocol/AccessPermission.hh"
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class DataBlock;
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class AbstractCacheEntry : public ReplaceableEntry
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{
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private:
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// The last access tick for the cache entry.
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Tick m_last_touch_tick;
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public:
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AbstractCacheEntry();
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virtual ~AbstractCacheEntry() = 0;
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// Get/Set permission of the entry
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AccessPermission getPermission() const;
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void changePermission(AccessPermission new_perm);
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using ReplaceableEntry::print;
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virtual void print(std::ostream& out) const = 0;
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// The methods below are those called by ruby runtime, add when it
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// is absolutely necessary and should all be virtual function.
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virtual DataBlock& getDataBlk()
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{ panic("getDataBlk() not implemented!"); }
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int validBlocks;
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virtual int& getNumValidBlocks()
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{
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return validBlocks;
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}
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// Functions for locking and unlocking the cache entry. These are required
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// for supporting atomic memory accesses.
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void setLocked(int context);
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void clearLocked();
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bool isLocked(int context) const;
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// Address of this block, required by CacheMemory
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Addr m_Address;
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// Holds info whether the address is locked.
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// Required for implementing LL/SC operations.
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int m_locked;
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AccessPermission m_Permission; // Access permission for this
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// block, required by CacheMemory
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// Get the last access Tick.
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Tick getLastAccess() { return m_last_touch_tick; }
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// Set the last access Tick.
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void setLastAccess(Tick tick) { m_last_touch_tick = tick; }
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// hardware transactional memory
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void setInHtmReadSet(bool val);
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void setInHtmWriteSet(bool val);
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bool getInHtmReadSet() const;
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bool getInHtmWriteSet() const;
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virtual void invalidateEntry() {}
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private:
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// hardware transactional memory
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bool m_htmInReadSet;
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bool m_htmInWriteSet;
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};
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inline std::ostream&
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operator<<(std::ostream& out, const AbstractCacheEntry& obj)
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{
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obj.print(out);
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out << std::flush;
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return out;
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}
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#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
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