4fdf61493b
HTMSequencer stats are already initialized in the constructor This is a bug from: [1]: https://gem5-review.googlesource.com/c/public/gem5/+/36478 Change-Id: Id7d9b11f45035a46af32584ed86470c65d2a80b6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51407 Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
122 lines
4.5 KiB
C++
122 lines
4.5 KiB
C++
/*
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* Copyright (c) 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_SYSTEM_HTMSEQUENCER_HH__
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#define __MEM_RUBY_SYSTEM_HTMSEQUENCER_HH__
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#include <cassert>
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#include <iostream>
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#include "mem/htm.hh"
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#include "mem/ruby/protocol/HtmCallbackMode.hh"
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#include "mem/ruby/protocol/HtmFailedInCacheReason.hh"
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#include "mem/ruby/system/RubyPort.hh"
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#include "mem/ruby/system/Sequencer.hh"
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#include "params/RubyHTMSequencer.hh"
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namespace gem5
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{
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namespace ruby
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{
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class HTMSequencer : public Sequencer
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{
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public:
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HTMSequencer(const RubyHTMSequencerParams &p);
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~HTMSequencer();
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// callback to acknowledge HTM requests and
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// notify cpu core when htm transaction fails in cache
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void htmCallback(Addr,
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const HtmCallbackMode,
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const HtmFailedInCacheReason);
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bool empty() const override;
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void print(std::ostream& out) const override;
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void wakeup() override;
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private:
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/**
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* Htm return code conversion
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*
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* This helper is a hack meant to convert the autogenerated ruby
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* enum (HtmFailedInCacheReason) to the manually defined one
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* (HtmCacheFailure). This is needed since the cpu code would
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* otherwise have to include the ruby generated headers in order
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* to handle the htm return code.
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*/
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HtmCacheFailure htmRetCodeConversion(const HtmFailedInCacheReason rc);
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void rubyHtmCallback(PacketPtr pkt, const HtmFailedInCacheReason fail_r);
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RequestStatus insertRequest(PacketPtr pkt,
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RubyRequestType primary_type,
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RubyRequestType secondary_type) override;
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// Private copy constructor and assignment operator
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HTMSequencer(const HTMSequencer& obj);
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HTMSequencer& operator=(const HTMSequencer& obj);
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// table/queue for hardware transactional memory commands
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// these do not have an address so a deque/queue is used instead.
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std::deque<SequencerRequest*> m_htmCmdRequestTable;
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Tick m_htmstart_tick;
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Counter m_htmstart_instruction;
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//! Histogram of cycle latencies of HTM transactions
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statistics::Histogram m_htm_transaction_cycles;
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//! Histogram of instruction lengths of HTM transactions
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statistics::Histogram m_htm_transaction_instructions;
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//! Causes for HTM transaction aborts
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statistics::Vector m_htm_transaction_abort_cause;
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};
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inline std::ostream&
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operator<<(std::ostream& out, const HTMSequencer& obj)
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{
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obj.print(out);
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out << std::flush;
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return out;
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}
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} // namespace ruby
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} // namespace gem5
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#endif // __MEM_RUBY_SYSTEM_HTMSEQUENCER_HH__
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