Faissal Sleiman 9195f1fbfd cpu: Change IEW DPRINTF to use IEW debug flag ...

IEW DPRINTF uses Decode debug flag, which appears to be a copying error. This
patch changes this to the IEW Debug flag.

2013-10-17 10:20:45 -05:00

..

base_dyn_inst.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

checker.cc

sim: Add the notion of clock domains to all ClockedObjects

2013-06-27 05:49:49 -04:00

checker.hh

cpu: Add header files for checker CPUs

2012-11-02 11:32:01 -05:00

comm.hh

O3: Pack the comm structures a bit better to reduce their size.

2012-09-25 11:49:40 -05:00

commit_impl.hh

o3cpu: commit: changes interrupt handling

2013-03-29 14:05:26 -05:00

commit.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

commit.hh

cpu: Fix a livelock in the o3 cpu.

2013-02-15 17:40:07 -05:00

cpu_policy.hh

cpu/o3: clean up rename map and free list

2013-10-15 14:22:44 -04:00

cpu.cc

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

cpu.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

decode_impl.hh

o3: fix tick used for renaming and issue with range selection

2013-02-15 17:40:09 -05:00

decode.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

decode.hh

cpu: Rewrite O3 draining to avoid stopping in microcode

2013-01-07 13:05:46 -05:00

dep_graph.hh

cpu: Rewrite O3 draining to avoid stopping in microcode

2013-01-07 13:05:46 -05:00

deriv.cc

branch predictor: move out of o3 and inorder cpus

2013-01-24 12:28:51 -06:00

deriv.hh

cpu: O3 add a header declaring the DerivO3CPU

2012-11-02 11:32:01 -05:00

dyn_inst_impl.hh

o3: fix tick used for renaming and issue with range selection

2013-02-15 17:40:09 -05:00

dyn_inst.cc

O3: Generaize the O3 IMPL class so it isn't split out by ISA.

2008-10-09 00:10:02 -07:00

dyn_inst.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

fetch_impl.hh

cpu: Fix a bug in the O3 CPU introduced by the cache line patch

2013-08-19 03:52:24 -04:00

fetch.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

fetch.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

free_list.cc

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

free_list.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

fu_pool.cc

cpu: Consider instructions waiting for FU completion in draining

2013-06-27 05:49:49 -04:00

fu_pool.hh

cpu: Consider instructions waiting for FU completion in draining

2013-06-27 05:49:49 -04:00

FuncUnitConfig.py

CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.

2010-11-15 14:04:04 -06:00

FUPool.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

iew_impl.hh

cpu: Change IEW DPRINTF to use IEW debug flag

2013-10-17 10:20:45 -05:00

iew.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

iew.hh

O3 IEW: Make incrWb and decrWb clearer

2013-01-19 15:14:54 -06:00

impl.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

inst_queue_impl.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

inst_queue.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

inst_queue.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

isa_specific.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

lsq_impl.hh

cpu: Dynamically instantiate O3 CPU LSQUnits

2013-09-11 15:34:50 -05:00

lsq_unit_impl.hh

cpu: Put in assertions to check for maximum supported LQ/SQ size

2013-10-17 10:20:45 -05:00

lsq_unit.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

lsq_unit.hh

cpu: Rewrite O3 draining to avoid stopping in microcode

2013-01-07 13:05:46 -05:00

lsq.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

lsq.hh

cpu: Dynamically instantiate O3 CPU LSQUnits

2013-09-11 15:34:50 -05:00

mem_dep_unit_impl.hh

cpu: Rewrite O3 draining to avoid stopping in microcode

2013-01-07 13:05:46 -05:00

mem_dep_unit.cc

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

mem_dep_unit.hh

cpu: Rewrite O3 draining to avoid stopping in microcode

2013-01-07 13:05:46 -05:00

O3Checker.py

cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy

2013-02-15 17:40:08 -05:00

O3CPU.py

arch/x86: add support for explicit CC register file

2013-10-15 14:22:44 -04:00

regfile.cc

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

regfile.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

rename_impl.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

rename_map.cc

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

rename_map.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

rename.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

rename.hh

cpu: Rewrite O3 draining to avoid stopping in microcode

2013-01-07 13:05:46 -05:00

rob_impl.hh

scons: Fix up numerous warnings about name shadowing

2013-02-19 05:56:06 -05:00

rob.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

rob.hh

cpu: Rewrite O3 draining to avoid stopping in microcode

2013-01-07 13:05:46 -05:00

SConscript

cpu/o3: clean up rename map and free list

2013-10-15 14:22:44 -04:00

SConsopts

cpu_models: get rid of cpu_models.py and move the stuff into SCons

2010-02-26 18:14:48 -08:00

scoreboard.cc

cpu/o3: clean up scoreboard object

2013-10-15 14:22:43 -04:00

scoreboard.hh

cpu/o3: clean up scoreboard object

2013-10-15 14:22:43 -04:00

store_set.cc

LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.

2011-08-19 15:08:07 -05:00

store_set.hh

LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.

2011-08-19 15:08:07 -05:00

thread_context_impl.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

thread_context.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

thread_context.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

thread_state.hh

cpu: Unify SimpleCPU and O3 CPU serialization code

2013-01-07 13:05:44 -05:00