Adrien Pesle 9181c2ea16 dev-arm: Fix Gicv2 distributor group register ...

For each bit in GICD_IGROUPR:
value 0 means corresponding irq is group0
value 1 means corresponding irq is group 1.

Change-Id: I15699d4bc89ff3df0e0bdb41154c0d0989dc2f63
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13555
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2018-10-17 14:47:14 +00:00

..

arch

arch: Explicitly specify the endianness in the generic mem helpers.

2018-10-12 23:58:58 +00:00

base

base: Avoid dividing by zero in Time::[gs]etTick.

2018-09-11 21:39:28 +00:00

cpu

cpu: Fix MinorCPU executing Crypto Instructions

2018-10-09 09:12:28 +00:00

dev

dev-arm: Fix Gicv2 distributor group register

2018-10-17 14:47:14 +00:00

doc

docs: Fix power model doxygen

2018-04-20 15:59:35 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

hsail-x86: fix gpu dynamic instruction error

2018-08-17 16:58:05 +00:00

kern

sim-se: Add /sys/devices/system/cpu/online file

2018-03-15 20:45:34 +00:00

learning_gem5

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

mem

mem-cache: Add missing includes in TreePLRU

2018-10-13 13:31:02 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

python: Fix call bug in @cxxMethod when override is True

2018-06-28 17:40:26 +00:00

sim

sim: Extend (UN)SERIALIZE_ARRAY to BitUnions

2018-10-01 08:16:33 +00:00

systemc

systemc: Get rid of leftovers from unimplemented warnings past.

2018-10-16 01:18:36 +00:00

unittest

base, mem: Disambiguate if an addr range is contained or overlaps

2018-06-19 14:24:25 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: Generalize building binaries.

2018-06-26 00:15:12 +00:00