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90bfbd9793e64b29d09f4ca4ee610ee08f82ea75
gem5/src/mem/ruby/system
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Nilay Vaish 90bfbd9793 ruby: network: convert to gem5 style stats
2013-09-06 16:21:35 -05:00
..
AbstractReplacementPolicy.hh
ruby: replace Time with Tick in replacement policy classes
2013-02-10 21:43:08 -06:00
BankedArray.cc
ruby banked array: do away with event scheduling
2012-10-15 17:27:15 -05:00
BankedArray.hh
ruby banked array: do away with event scheduling
2012-10-15 17:27:15 -05:00
Cache.py
ruby: replaces Time with Cycles in many places
2013-02-10 21:26:24 -06:00
CacheMemory.cc
ruby: add stats to .sm files, remove cache profiler
2013-05-21 11:31:31 -05:00
CacheMemory.hh
ruby: add stats to .sm files, remove cache profiler
2013-05-21 11:31:31 -05:00
DirectoryMemory.cc
ruby: converts sparse memory stats to gem5 style
2013-09-06 16:21:28 -05:00
DirectoryMemory.hh
ruby: converts sparse memory stats to gem5 style
2013-09-06 16:21:28 -05:00
DirectoryMemory.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
DMASequencer.cc
ruby: enable multiple clock domains
2013-02-10 21:43:17 -06:00
DMASequencer.hh
scons: Fix warnings issued by clang 3.2svn (XCode 4.6)
2013-02-19 05:56:08 -05:00
LRUPolicy.hh
ruby: replace Time with Tick in replacement policy classes
2013-02-10 21:43:08 -06:00
MachineID.hh
Ruby: Fix compilation errors on gcc 4.7 and clang 3.2
2013-02-14 12:24:51 -05:00
MemoryControl.cc
ruby: improved support for functional accesses
2012-10-15 17:51:57 -05:00
MemoryControl.hh
ruby: stats: use gem5's stats for cache and memory controllers
2013-06-09 07:29:59 -05:00
MemoryControl.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
MemoryNode.cc
ruby: style pass
2010-03-22 18:43:53 -07:00
MemoryNode.hh
ruby: replace Time with Cycles in Memory Controller
2013-02-10 21:26:25 -06:00
MemoryVector.hh
Ruby: Use uint32_t instead of uint32 everywhere
2012-09-11 09:24:45 -05:00
PerfectCacheMemory.hh
Ruby: remove config information from ruby.stats
2012-07-12 08:39:19 -05:00
PersistentTable.cc
ruby: get rid of the Map class
2010-06-10 23:17:07 -07:00
PersistentTable.hh
Ruby: remove config information from ruby.stats
2012-07-12 08:39:19 -05:00
PseudoLRUPolicy.hh
ruby: replace Time with Tick in replacement policy classes
2013-02-10 21:43:08 -06:00
RubyMemoryControl.cc
ruby: restrict Address to being a type and not a variable name
2013-06-18 16:58:33 -05:00
RubyMemoryControl.hh
ruby: stats: use gem5's stats for cache and memory controllers
2013-06-09 07:29:59 -05:00
RubyMemoryControl.py
sim: Add the notion of clock domains to all ClockedObjects
2013-06-27 05:49:49 -04:00
RubyPort.cc
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
RubyPort.hh
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
RubyPortProxy.cc
MEM: Add port proxies instead of non-structural ports
2012-01-17 12:55:08 -06:00
RubyPortProxy.hh
MEM: Add port proxies instead of non-structural ports
2012-01-17 12:55:08 -06:00
RubySystem.py
config: Remove redundant explicit setting of default clocks
2013-06-27 05:49:49 -04:00
SConscript
ruby: banked cache array resource model
2012-07-10 22:51:54 -07:00
Sequencer.cc
ruby: profiler: lots of inter-related changes
2013-06-25 00:32:03 -05:00
Sequencer.hh
ruby: profiler: lots of inter-related changes
2013-06-25 00:32:03 -05:00
Sequencer.py
ruby: remove the functional copy of memory in se mode
2013-03-06 21:53:57 -06:00
SparseMemory.cc
ruby: converts sparse memory stats to gem5 style
2013-09-06 16:21:28 -05:00
SparseMemory.hh
ruby: converts sparse memory stats to gem5 style
2013-09-06 16:21:28 -05:00
System.cc
ruby: network: convert to gem5 style stats
2013-09-06 16:21:35 -05:00
System.hh
ruby: network: convert to gem5 style stats
2013-09-06 16:21:35 -05:00
TBETable.hh
ruby: replace Time with Cycles (final patch in the series)
2013-02-10 21:43:10 -06:00
TimerTable.cc
ruby: consumer: avoid using receiver side clock
2013-03-22 15:53:26 -05:00
TimerTable.hh
ruby: replace Time with Cycles (final patch in the series)
2013-02-10 21:43:10 -06:00
WireBuffer.cc
ruby: consumer: avoid using receiver side clock
2013-03-22 15:53:26 -05:00
WireBuffer.hh
scons: Add warning for missing declarations
2013-02-19 05:56:07 -05:00
WireBuffer.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00