Giacomo Travaglini 9b6f0a9768 arch-arm: Remove floatReg operand type ...

Change-Id: I87553257ce9c42d0e2514d5a1f010bc6e2e7f21e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15604
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2019-01-25 12:55:27 +00:00

..

arch

arch-arm: Remove floatReg operand type

2019-01-25 12:55:27 +00:00

base

base: arch: Get rid of the now unused FloatRegVal type.

2019-01-24 23:42:22 +00:00

cpu

cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

2019-01-25 12:55:27 +00:00

dev

dev-arm: fix --generate-dtb for ARM

2019-01-24 14:12:35 +00:00

doc

docs: Fix power model doxygen

2018-04-20 15:59:35 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

2019-01-16 20:27:47 +00:00

kern

sim-se: add syscalls related to polling

2019-01-22 02:05:48 +00:00

learning_gem5

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

mem

mem-ruby: Fix missing TBE allocation and deallocation

2019-01-23 00:31:11 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

python: Always throw TypeError on slave-slave connections

2019-01-25 12:46:15 +00:00

sim

sim-se add readv and modifies writev

2019-01-22 02:14:47 +00:00

systemc

systemc: Fix TLM related includes.

2019-01-23 09:52:52 +00:00

unittest

misc: updated shabang for python script

2019-01-11 17:41:02 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: add helpers to access GDB XML description files

2019-01-22 11:35:12 +00:00