12502d2529
JIRA: https://gem5.atlassian.net/browse/GEM5-1121 Change-Id: I7544823710d9a63146d18d4fe9b7c969312ad4d7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53627 Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
143 lines
5.3 KiB
Python
143 lines
5.3 KiB
Python
# Copyright (c) 2021 Arm Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import sst
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import sys
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import os
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from sst import UnitAlgebra
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cache_link_latency = "1ps"
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kernel = "vmlinux_exit.arm64"
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cpu_clock_rate = "3GHz"
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# gem5 will send requests to physical addresses of range [0x80000000, inf) to memory
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# currently, we do not subtract 0x80000000 from the request's address to get the "real" address
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# so, the mem_size would always be 2GiB larger than the desired memory size
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memory_size_gem5 = "4GiB"
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memory_size_sst = "16GiB"
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addr_range_end = UnitAlgebra(memory_size_sst).getRoundedValue()
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l1_params = {
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"access_latency_cycles" : "1",
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"cache_frequency" : cpu_clock_rate,
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"replacement_policy" : "lru",
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"coherence_protocol" : "MESI",
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"associativity" : "4",
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"cache_line_size" : "64",
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"cache_size" : "4 KiB",
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"L1" : "1",
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}
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gem5_command = f" ../../configs/example/sst/arm_fs.py \
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--kernel {kernel} \
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--cpu-clock-rate {cpu_clock_rate} \
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--memory-size {memory_size_gem5}"
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cpu_params = {
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"frequency": cpu_clock_rate,
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"cmd": gem5_command,
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}
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gem5_node = sst.Component("gem5_node", "gem5.gem5Component")
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gem5_node.addParams(cpu_params)
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cache_bus = sst.Component("cache_bus", "memHierarchy.Bus")
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cache_bus.addParams( { "bus_frequency" : cpu_clock_rate } )
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system_port = gem5_node.setSubComponent("system_port", "gem5.gem5Bridge", 0) # for initialization
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system_port.addParams({
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"response_receiver_name": "system.system_outgoing_bridge",
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"mem_size": memory_size_sst
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})
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cache_port = gem5_node.setSubComponent("cache_port", "gem5.gem5Bridge", 0) # SST -> gem5
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cache_port.addParams({
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"response_receiver_name": "system.memory_outgoing_bridge",
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"mem_size": memory_size_sst
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})
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# L1 cache
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l1_cache = sst.Component("l1_cache", "memHierarchy.Cache")
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l1_cache.addParams(l1_params)
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# Memory
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memctrl = sst.Component("memory", "memHierarchy.MemController")
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memctrl.addParams({
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"debug" : "0",
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"clock" : "1GHz",
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"request_width" : "64",
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"addr_range_end" : addr_range_end, # should be changed accordingly to memory_size_sst
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})
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memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem")
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memory.addParams({
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"access_time" : "30ns",
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"mem_size" : memory_size_sst
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})
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# Connections
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# cpu <-> L1
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cpu_cache_link = sst.Link("cpu_l1_cache_link")
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cpu_cache_link.connect(
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(cache_port, "port", cache_link_latency),
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(cache_bus, "high_network_0", cache_link_latency)
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)
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system_cache_link = sst.Link("system_cache_link")
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system_cache_link.connect(
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(system_port, "port", cache_link_latency),
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(cache_bus, "high_network_1", cache_link_latency)
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)
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cache_bus_cache_link = sst.Link("cache_bus_cache_link")
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cache_bus_cache_link.connect(
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(cache_bus, "low_network_0", cache_link_latency),
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(l1_cache, "high_network_0", cache_link_latency)
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)
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# L1 <-> mem
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cache_mem_link = sst.Link("l1_cache_mem_link")
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cache_mem_link.connect(
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(l1_cache, "low_network_0", cache_link_latency),
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(memctrl, "direct_link", cache_link_latency)
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)
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# enable Statistics
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stat_params = { "rate" : "0ns" }
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sst.setStatisticLoadLevel(5)
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sst.setStatisticOutput("sst.statOutputTXT", {"filepath" : "./sst-stats.txt"})
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sst.enableAllStatisticsForComponentName("l1_cache", stat_params)
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sst.enableAllStatisticsForComponentName("memory", stat_params)
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