Change-Id: I94d6f5b172ab71ee8bedea854e1db9711748f313 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49451 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
300 lines
8.2 KiB
Python
300 lines
8.2 KiB
Python
# Copyright 2004-2006 The Regents of The University of Michigan
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# Copyright 2010-20013 Advanced Micro Devices, Inc.
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# Copyright 2013 Mark D. Hill and David A. Wood
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# Copyright 2017-2020 ARM Limited
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# Copyright 2021 Google, Inc.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import argparse
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import importlib
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import os.path
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import sys
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import importer
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from code_formatter import code_formatter
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parser = argparse.ArgumentParser()
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parser.add_argument('modpath', help='module the simobject belongs to')
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parser.add_argument('cxx_config_cc', help='cxx config cc file to generate')
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args = parser.parse_args()
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basename = os.path.basename(args.cxx_config_cc)
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sim_object_name = os.path.splitext(basename)[0]
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importer.install()
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module = importlib.import_module(args.modpath)
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sim_object = getattr(module, sim_object_name)
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from m5.params import isSimObjectClass
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import m5.params
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code = code_formatter()
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entry_class = 'CxxConfigDirectoryEntry_%s' % sim_object_name
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param_class = '%sCxxConfigParams' % sim_object_name
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def cxx_bool(b):
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return 'true' if b else 'false'
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code('#include "params/%s.hh"' % sim_object_name)
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for param in sim_object._params.values():
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if isSimObjectClass(param.ptype):
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code('#include "%s"' % param.ptype._value_dict['cxx_header'])
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code('#include "params/%s.hh"' % param.ptype.__name__)
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else:
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param.ptype.cxx_ini_predecls(code)
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code('''#include "${{sim_object._value_dict['cxx_header']}}"
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#include "base/str.hh"
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#include "cxx_config/${sim_object_name}.hh"
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namespace gem5
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{
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${param_class}::DirectoryEntry::DirectoryEntry()
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{
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''')
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code.indent()
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for param in sim_object._params.values():
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is_vector = isinstance(param, m5.params.VectorParamDesc)
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is_simobj = issubclass(param.ptype, m5.SimObject.SimObject)
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code('parameters["%s"] = new ParamDesc("%s", %s, %s);' %
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(param.name, param.name, cxx_bool(is_vector),
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cxx_bool(is_simobj)));
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for port in sim_object._ports.values():
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is_vector = isinstance(port, m5.params.VectorPort)
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is_requestor = port.role == 'GEM5 REQUESTOR'
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code('ports["%s"] = new PortDesc("%s", %s, %s);' %
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(port.name, port.name, cxx_bool(is_vector),
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cxx_bool(is_requestor)))
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code.dedent()
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code('''}
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bool
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${param_class}::setSimObject(const std::string &name, SimObject *simObject)
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{
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bool ret = true;
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if (false) {
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''')
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code.indent()
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for param in sim_object._params.values():
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is_vector = isinstance(param, m5.params.VectorParamDesc)
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is_simobj = issubclass(param.ptype, m5.SimObject.SimObject)
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if is_simobj and not is_vector:
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code('} else if (name == "${{param.name}}") {')
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code.indent()
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code('this->${{param.name}} = '
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'dynamic_cast<${{param.ptype.cxx_type}}>(simObject);')
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code('if (simObject && !this->${{param.name}})')
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code(' ret = false;')
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code.dedent()
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code.dedent()
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code('''
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} else {
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ret = false;
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}
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return ret;
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}
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bool
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${param_class}::setSimObjectVector(const std::string &name,
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const std::vector<SimObject *> &simObjects)
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{
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bool ret = true;
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if (false) {
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''')
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code.indent()
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for param in sim_object._params.values():
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is_vector = isinstance(param, m5.params.VectorParamDesc)
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is_simobj = issubclass(param.ptype, m5.SimObject.SimObject)
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if is_simobj and is_vector:
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code('} else if (name == "${{param.name}}") {')
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code.indent()
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code('this->${{param.name}}.clear();')
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code('for (auto i = simObjects.begin(); '
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'ret && i != simObjects.end(); i ++)')
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code('{')
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code.indent()
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code('${{param.ptype.cxx_type}} object = '
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'dynamic_cast<${{param.ptype.cxx_type}}>(*i);')
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code('if (*i && !object)')
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code(' ret = false;')
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code('else')
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code(' this->${{param.name}}.push_back(object);')
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code.dedent()
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code('}')
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code.dedent()
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code.dedent()
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code('''
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} else {
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ret = false;
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}
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return ret;
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}
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void
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${param_class}::setName(const std::string &name_)
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{
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this->name = name_;
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}
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bool
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${param_class}::setParam(const std::string &name,
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const std::string &value, const Flags flags)
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{
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bool ret = true;
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if (false) {
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''')
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code.indent()
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for param in sim_object._params.values():
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is_vector = isinstance(param, m5.params.VectorParamDesc)
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is_simobj = issubclass(param.ptype, m5.SimObject.SimObject)
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if not is_simobj and not is_vector:
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code('} else if (name == "${{param.name}}") {')
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code.indent()
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param.ptype.cxx_ini_parse(code,
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'value', 'this->%s' % param.name, 'ret =')
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code.dedent()
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code.dedent()
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code('''
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} else {
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ret = false;
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}
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return ret;
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}
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bool
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${param_class}::setParamVector(const std::string &name,
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const std::vector<std::string> &values, const Flags flags)
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{
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bool ret = true;
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if (false) {
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''')
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code.indent()
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for param in sim_object._params.values():
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is_vector = isinstance(param, m5.params.VectorParamDesc)
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is_simobj = issubclass(param.ptype, m5.SimObject.SimObject)
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if not is_simobj and is_vector:
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code('} else if (name == "${{param.name}}") {')
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code.indent()
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code('${{param.name}}.clear();')
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code('for (auto i = values.begin(); '
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'ret && i != values.end(); i ++)')
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code('{')
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code.indent()
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code('${{param.ptype.cxx_type}} elem;')
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param.ptype.cxx_ini_parse(code,
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'*i', 'elem', 'ret =')
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code('if (ret)')
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code(' this->${{param.name}}.push_back(elem);')
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code.dedent()
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code('}')
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code.dedent()
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code.dedent()
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code('''
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} else {
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ret = false;
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}
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return ret;
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}
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bool
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${param_class}::setPortConnectionCount(const std::string &name,
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unsigned int count)
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{
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bool ret = true;
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if (false) {
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''')
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code.indent()
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for port in sim_object._ports.values():
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code('} else if (name == "${{port.name}}") {')
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code(' this->port_${{port.name}}_connection_count = count;')
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code.dedent()
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code('''
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} else {
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ret = false;
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}
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return ret;
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}
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SimObject *
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${param_class}::simObjectCreate()
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{
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''')
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code.indent()
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if hasattr(sim_object, 'abstract') and sim_object.abstract:
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code('return nullptr;')
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else:
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code('return this->create();')
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code.dedent()
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code('''}
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} // namespace gem5
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''')
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code.write(args.cxx_config_cc)
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