2343ee2705
Change-Id: I1b648914d353672076d903ed581aa61cdd7c1d0f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39562 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
75 lines
2.7 KiB
C++
75 lines
2.7 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/intr_control.hh"
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "debug/IntrControl.hh"
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#include "sim/sim_object.hh"
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IntrControl::IntrControl(const Params &p)
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: SimObject(p), sys(p.sys)
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{}
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void
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IntrControl::post(int cpu_id, int int_num, int index)
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{
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DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
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auto *tc = sys->threads[cpu_id];
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tc->getCpuPtr()->postInterrupt(tc->threadId(), int_num, index);
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}
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void
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IntrControl::clear(int cpu_id, int int_num, int index)
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{
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DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
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auto *tc = sys->threads[cpu_id];
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tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_num, index);
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}
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void
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IntrControl::clearAll(int cpu_id)
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{
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DPRINTF(IntrControl, "Clear all pending interrupts for CPU %d\n", cpu_id);
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auto *tc = sys->threads[cpu_id];
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tc->getCpuPtr()->clearInterrupts(tc->threadId());
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}
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bool
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IntrControl::havePosted(int cpu_id) const
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{
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DPRINTF(IntrControl, "Check pending interrupts for CPU %d\n", cpu_id);
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auto *tc = sys->threads[cpu_id];
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return tc->getCpuPtr()->checkInterrupts(tc->threadId());
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}
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