2e5da92295
Use the system object to allocate physical memory instead of manually placing certain structures and then forcing the system to start other allocations after them in physical memory. Change-Id: Ie18c81645c3b648c64a6d7a649a0e50f7028f344 Reviewed-on: https://gem5-review.googlesource.com/7346 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
232 lines
7.6 KiB
C++
232 lines
7.6 KiB
C++
/*
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* Copyright (c) 2014 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Alexandru Dutu
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*/
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/**
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* @file
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* Definitions of page table
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*/
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#include <string>
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#include "arch/isa_traits.hh"
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "debug/MMU.hh"
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#include "mem/multi_level_page_table.hh"
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#include "mem/page_table.hh"
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using namespace std;
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using namespace TheISA;
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template <class ISAOps>
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MultiLevelPageTable<ISAOps>::MultiLevelPageTable(
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const std::string &__name, uint64_t _pid, System *_sys,
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Addr pageSize, const std::vector<uint8_t> &layout)
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: EmulationPageTable(__name, _pid, pageSize), system(_sys),
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logLevelSize(layout), numLevels(logLevelSize.size())
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{
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}
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template <class ISAOps>
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MultiLevelPageTable<ISAOps>::~MultiLevelPageTable()
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{
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}
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template <class ISAOps>
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void
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MultiLevelPageTable<ISAOps>::initState(ThreadContext* tc)
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{
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/* setting first level of the page table */
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uint64_t log_req_size = floorLog2(sizeof(PageTableEntry)) +
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logLevelSize[numLevels - 1];
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assert(log_req_size >= PageShift);
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uint64_t npages = 1 << (log_req_size - PageShift);
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Addr _basePtr = system->allocPhysPages(npages);
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PortProxy &p = system->physProxy;
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p.memsetBlob(_basePtr, 0, npages << PageShift);
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}
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template <class ISAOps>
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void
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MultiLevelPageTable<ISAOps>::walk(Addr vaddr, bool allocate, Addr &PTE_addr)
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{
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std::vector<uint64_t> offsets = pTableISAOps.getOffsets(vaddr);
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Addr level_base = _basePtr;
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for (int i = numLevels - 1; i > 0; i--) {
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Addr entry_addr = (level_base<<PageShift) +
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offsets[i] * sizeof(PageTableEntry);
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PortProxy &p = system->physProxy;
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PageTableEntry entry = p.read<PageTableEntry>(entry_addr);
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Addr next_entry_pnum = pTableISAOps.getPnum(entry);
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if (next_entry_pnum == 0) {
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fatal_if(!allocate, "Page fault while walking the page table.");
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uint64_t log_req_size = floorLog2(sizeof(PageTableEntry)) +
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logLevelSize[i - 1];
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assert(log_req_size >= PageShift);
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uint64_t npages = 1 << (log_req_size - PageShift);
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DPRINTF(MMU, "Allocating %d pages needed for entry in level %d\n",
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npages, i - 1);
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/* allocate new entry */
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Addr next_entry_paddr = system->allocPhysPages(npages);
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p.memsetBlob(next_entry_paddr, 0, npages << PageShift);
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next_entry_pnum = next_entry_paddr >> PageShift;
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pTableISAOps.setPnum(entry, next_entry_pnum);
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pTableISAOps.setPTEFields(entry);
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p.write<PageTableEntry>(entry_addr, entry);
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}
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DPRINTF(MMU, "Level %d base: %d offset: %d entry: %d\n",
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i, level_base, offsets[i], next_entry_pnum);
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level_base = next_entry_pnum;
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}
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PTE_addr = (level_base << PageShift) +
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offsets[0] * sizeof(PageTableEntry);
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DPRINTF(MMU, "Returning PTE_addr: %x\n", PTE_addr);
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}
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template <class ISAOps>
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void
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MultiLevelPageTable<ISAOps>::map(Addr vaddr, Addr paddr,
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int64_t size, uint64_t flags)
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{
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EmulationPageTable::map(vaddr, paddr, size, flags);
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PortProxy &p = system->physProxy;
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while (size > 0) {
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Addr PTE_addr;
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walk(vaddr, true, PTE_addr);
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PageTableEntry PTE = p.read<PageTableEntry>(PTE_addr);
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pTableISAOps.setPnum(PTE, paddr >> PageShift);
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uint64_t PTE_flags = 0;
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if (flags & NotPresent)
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PTE_flags |= TheISA::PTE_NotPresent;
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if (flags & Uncacheable)
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PTE_flags |= TheISA::PTE_Uncacheable;
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if (flags & ReadOnly)
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PTE_flags |= TheISA::PTE_ReadOnly;
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pTableISAOps.setPTEFields(PTE, PTE_flags);
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p.write<PageTableEntry>(PTE_addr, PTE);
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DPRINTF(MMU, "New mapping: %#x-%#x\n", vaddr, paddr);
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size -= pageSize;
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vaddr += pageSize;
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paddr += pageSize;
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}
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}
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template <class ISAOps>
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void
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MultiLevelPageTable<ISAOps>::remap(Addr vaddr, int64_t size, Addr new_vaddr)
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{
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EmulationPageTable::remap(vaddr, size, new_vaddr);
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PortProxy &p = system->physProxy;
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while (size > 0) {
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Addr PTE_addr;
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walk(vaddr, false, PTE_addr);
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PageTableEntry PTE = p.read<PageTableEntry>(PTE_addr);
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Addr paddr = pTableISAOps.getPnum(PTE);
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fatal_if(paddr == 0, "Page fault while remapping");
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/* unmapping vaddr */
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pTableISAOps.setPnum(PTE, 0);
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p.write<PageTableEntry>(PTE_addr, PTE);
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/* maping new_vaddr */
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Addr new_PTE_addr;
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walk(new_vaddr, true, new_PTE_addr);
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PageTableEntry new_PTE = p.read<PageTableEntry>(new_PTE_addr);
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pTableISAOps.setPnum(new_PTE, paddr >> PageShift);
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pTableISAOps.setPTEFields(new_PTE);
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p.write<PageTableEntry>(new_PTE_addr, new_PTE);
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DPRINTF(MMU, "Remapping: %#x-%#x\n", vaddr, new_PTE_addr);
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size -= pageSize;
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vaddr += pageSize;
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new_vaddr += pageSize;
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}
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}
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template <class ISAOps>
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void
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MultiLevelPageTable<ISAOps>::unmap(Addr vaddr, int64_t size)
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{
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EmulationPageTable::unmap(vaddr, size);
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PortProxy &p = system->physProxy;
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while (size > 0) {
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Addr PTE_addr;
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walk(vaddr, false, PTE_addr);
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PageTableEntry PTE = p.read<PageTableEntry>(PTE_addr);
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Addr paddr = pTableISAOps.getPnum(PTE);
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fatal_if(paddr == 0,
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"PageTable::allocate: address %#x not mapped", vaddr);
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pTableISAOps.setPnum(PTE, 0);
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p.write<PageTableEntry>(PTE_addr, PTE);
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DPRINTF(MMU, "Unmapping: %#x\n", vaddr);
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size -= pageSize;
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vaddr += pageSize;
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}
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}
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template <class ISAOps>
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void
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MultiLevelPageTable<ISAOps>::serialize(CheckpointOut &cp) const
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{
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EmulationPageTable::serialize(cp);
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/** Since, the page table is stored in system memory
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* which is serialized separately, we will serialize
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* just the base pointer
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*/
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paramOut(cp, "ptable.pointer", _basePtr);
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}
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template <class ISAOps>
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void
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MultiLevelPageTable<ISAOps>::unserialize(CheckpointIn &cp)
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{
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EmulationPageTable::unserialize(cp);
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paramIn(cp, "ptable.pointer", _basePtr);
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}
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