d207e9ccee
Replacement policies (LRU, Random) are currently considered as array indexing methods, but have completely different functionalities: - Array indexers determine the possible locations for block allocation. This information is used to generate replacement candidates when conflicts happen. - Replacement policies determine which of the replacement candidates should be evicted to make room for new allocations. For this reason, they were split into different classes. Advantages: - Easier and more straightforward to implement other replacement policies (RRIP, LFU, ARC, ...) - Allow easier future implementation of cache organization schemes As now we can't assure the use of sets, the previous way to create a true LRU is not viable. Now a timestamp_bits parameter controls how many bits are dedicated for the timestamp, and a true LRU can be achieved through an infinite number of bits (although a few bits suffice in practice). Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda Reviewed-on: https://gem5-review.googlesource.com/8501 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
120 lines
5.4 KiB
Python
120 lines
5.4 KiB
Python
# Copyright (c) 2012-2013, 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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# Andreas Hansson
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from m5.params import *
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from m5.proxy import *
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from MemObject import MemObject
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from Prefetcher import BasePrefetcher
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from ReplacementPolicies import *
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from Tags import *
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class BaseCache(MemObject):
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type = 'BaseCache'
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abstract = True
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cxx_header = "mem/cache/base.hh"
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size = Param.MemorySize("Capacity")
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assoc = Param.Unsigned("Associativity")
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tag_latency = Param.Cycles("Tag lookup latency")
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data_latency = Param.Cycles("Data access latency")
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response_latency = Param.Cycles("Latency for the return path on a miss");
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warmup_percentage = Param.Percent(0,
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"Percentage of tags to be touched to warm up the cache")
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max_miss_count = Param.Counter(0,
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"Number of misses to handle before calling exit")
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mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
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demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
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tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
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write_buffers = Param.Unsigned(8, "Number of write buffers")
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is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
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prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
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prefetch_on_access = Param.Bool(False,
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"Notify the hardware prefetcher on every access (not just misses)")
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tags = Param.BaseTags(BaseSetAssoc(), "Tag store")
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replacement_policy = Param.BaseReplacementPolicy(LRURP(),
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"Replacement policy")
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sequential_access = Param.Bool(False,
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"Whether to access tags and data sequentially")
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cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
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mem_side = MasterPort("Downstream port closer to memory")
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addr_ranges = VectorParam.AddrRange([AllMemory],
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"Address range for the CPU-side port (to allow striping)")
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system = Param.System(Parent.any, "System we belong to")
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# Enum for cache clusivity, currently mostly inclusive or mostly
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# exclusive.
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class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
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class Cache(BaseCache):
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type = 'Cache'
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cxx_header = 'mem/cache/cache.hh'
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# Control whether this cache should be mostly inclusive or mostly
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# exclusive with respect to upstream caches. The behaviour on a
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# fill is determined accordingly. For a mostly inclusive cache,
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# blocks are allocated on all fill operations. Thus, L1 caches
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# should be set as mostly inclusive even if they have no upstream
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# caches. In the case of a mostly exclusive cache, fills are not
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# allocating unless they came directly from a non-caching source,
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# e.g. a table walker. Additionally, on a hit from an upstream
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# cache a line is dropped for a mostly exclusive cache.
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clusivity = Param.Clusivity('mostly_incl',
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"Clusivity with upstream cache")
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# Determine if this cache sends out writebacks for clean lines, or
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# simply clean evicts. In cases where a downstream cache is mostly
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# exclusive with respect to this cache (acting as a victim cache),
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# the clean writebacks are essential for performance. In general
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# this should be set to True for anything but the last-level
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# cache.
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writeback_clean = Param.Bool(False, "Writeback clean lines")
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