Andreas Hansson a00383a40a mem: Track DRAM read/write switching and add hysteresis ...

This patch adds stats for tracking the number of reads/writes per bus
turn around, and also adds hysteresis to the write-to-read switching
to ensure that the queue does not oscilate around the low threshold.

2014-03-23 11:12:14 -04:00

..

arch

arm: m5ops readfile64 args broken, offset coming through garbage

2014-03-23 11:11:34 -04:00

base

base: Fix error message time unit (cycle -> tick)

2014-03-23 11:11:32 -04:00

cpu

cpu: DRAM Traffic Generator

2014-03-23 11:11:58 -04:00

dev

dev: Fix IsaFake's cxx_header setting

2014-03-23 11:11:37 -04:00

doc

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

kern

sim: Add openat/fstatat syscalls and fix mremap

2014-01-24 15:29:30 -06:00

mem

mem: Track DRAM read/write switching and add hysteresis

2014-03-23 11:12:14 -04:00

proto

mem: Edit proto Packet and enhance the python script

2014-03-07 15:56:23 -05:00

python

misc: Fix -q (quiet) flag

2014-03-23 11:11:49 -04:00

sim

scons: Fixes uninitialized warnings issued by clang

2014-03-07 15:56:23 -05:00

unittest

unittest: Fix build errors

2014-01-30 12:21:58 -06:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

cpu: allow the fetch buffer to be smaller than a cache line

2013-11-15 13:21:15 -05:00