893533a126
This patch adds a parameter to the BaseCache to enable a read-only cache, for example for the instruction cache, or table-walker cache (not for x86). A number of checks are put in place in the code to ensure a read-only cache does not end up with dirty data. A follow-on patch adds suitable read requests to allow a read-only cache to explicitly ask for clean data.
85 lines
3.9 KiB
Python
85 lines
3.9 KiB
Python
# Copyright (c) 2012-2013, 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.params import *
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from m5.proxy import *
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from MemObject import MemObject
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from Prefetcher import BasePrefetcher
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from Tags import *
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class BaseCache(MemObject):
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type = 'BaseCache'
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cxx_header = "mem/cache/base.hh"
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size = Param.MemorySize("Capacity")
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assoc = Param.Unsigned("Associativity")
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hit_latency = Param.Cycles("Hit latency")
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response_latency = Param.Cycles("Latency for the return path on a miss");
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max_miss_count = Param.Counter(0,
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"Number of misses to handle before calling exit")
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mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
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demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
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tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
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write_buffers = Param.Unsigned(8, "Number of write buffers")
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forward_snoops = Param.Bool(True,
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"Forward snoops from mem side to cpu side")
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is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)")
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is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
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prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
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prefetch_on_access = Param.Bool(False,
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"Notify the hardware prefetcher on every access (not just misses)")
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tags = Param.BaseTags(LRU(), "Tag store (replacement policy)")
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sequential_access = Param.Bool(False,
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"Whether to access tags and data sequentially")
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cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
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mem_side = MasterPort("Downstream port closer to memory")
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addr_ranges = VectorParam.AddrRange([AllMemory],
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"Address range for the CPU-side port (to allow striping)")
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system = Param.System(Parent.any, "System we belong to")
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