Nilay Vaish c80af04d7d x86: Fix switching of CPUs ...

This patch prevents creation of interrupt controller for
cpus that will be switched in later

2012-03-01 11:37:02 -06:00

..

Benchmarks.py

configs: fix minor config bugs posted on the mailing list

2012-02-12 17:18:53 -06:00

CacheConfig.py

x86: Fix switching of CPUs

2012-03-01 11:37:02 -06:00

Caches.py

O3: Remove hardcoded tgts_per_mshr in O3CPU.py.

2011-12-01 00:15:22 -08:00

cpu2000.py

cpu2000: Add missing art benchmark to all

2012-01-09 18:08:20 -06:00

FSConfig.py

Make the IO bridge accept address headed to all the local APICs.

2012-02-26 15:33:07 -08:00

O3_ARM_v7a.py

prefetcher: Make prefetcher a sim object instead of it being a parameter on cache

2012-02-12 16:07:38 -06:00

Options.py

Config: make option ruby available always

2012-03-01 11:36:59 -06:00

Simulation.py

SE/FS: Get rid of FULL_SYSTEM in the configs directory

2012-01-28 07:24:50 -08:00

SysPaths.py

make rcS files read from the m5 source directory, not /dist.

2006-11-08 14:10:25 -05:00