859c1c6332
Change-Id: Iac3f9bb546121c73e6e73a0377d2a917c40df5f8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25452 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
125 lines
3.7 KiB
C++
125 lines
3.7 KiB
C++
/*
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* Copyright (c) 2006-2007 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_SPARC_INSTS_MICRO_HH__
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#define __ARCH_SPARC_INSTS_MICRO_HH__
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#include "arch/sparc/insts/static_inst.hh"
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namespace SparcISA
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{
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class SparcMacroInst : public SparcStaticInst
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{
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protected:
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const uint32_t numMicroops;
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// Constructor.
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SparcMacroInst(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, uint32_t _numMicroops) :
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SparcStaticInst(mnem, _machInst, __opClass),
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numMicroops(_numMicroops)
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{
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assert(numMicroops);
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microops = new StaticInstPtr[numMicroops];
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flags[IsMacroop] = true;
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}
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~SparcMacroInst()
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{
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delete [] microops;
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}
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std::string generateDisassembly(
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Addr pc, const SymbolTable *symtab) const override;
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StaticInstPtr *microops;
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StaticInstPtr
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fetchMicroop(MicroPC upc) const override
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{
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assert(upc < numMicroops);
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return microops[upc];
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}
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Fault
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execute(ExecContext *, Trace::InstRecord *) const override
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{
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panic("Tried to execute a macroop directly!\n");
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}
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Fault
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initiateAcc(ExecContext *, Trace::InstRecord *) const override
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{
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panic("Tried to execute a macroop directly!\n");
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}
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Fault
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completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const override
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{
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panic("Tried to execute a macroop directly!\n");
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}
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};
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class SparcMicroInst : public SparcStaticInst
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{
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protected:
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// Constructor.
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SparcMicroInst(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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SparcStaticInst(mnem, _machInst, __opClass)
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{
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flags[IsMicroop] = true;
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}
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void
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advancePC(SparcISA::PCState &pcState) const override
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{
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if (flags[IsLastMicroop])
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pcState.uEnd();
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else
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pcState.uAdvance();
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}
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};
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class SparcDelayedMicroInst : public SparcMicroInst
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{
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protected:
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// Constructor.
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SparcDelayedMicroInst(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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SparcMicroInst(mnem, _machInst, __opClass)
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{
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flags[IsDelayedCommit] = true;
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}
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};
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}
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#endif // __ARCH_SPARC_INSTS_MICRO_HH__
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