8590243fef
The HW Prefetcher of a cache can now listen events from their associated CPUs and from its own cache. Change-Id: I28aecd8faf8ed44be94464d84485bd1cea2efae3 Reviewed-on: https://gem5-review.googlesource.com/c/14155 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
136 lines
4.7 KiB
C++
136 lines
4.7 KiB
C++
/*
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* Copyright (c) 2014-2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Mitch Hayenga
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*/
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#ifndef __MEM_CACHE_PREFETCH_QUEUED_HH__
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#define __MEM_CACHE_PREFETCH_QUEUED_HH__
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#include <cstdint>
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#include <list>
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#include <utility>
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#include "base/statistics.hh"
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#include "base/types.hh"
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#include "mem/cache/prefetch/base.hh"
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#include "mem/packet.hh"
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struct QueuedPrefetcherParams;
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class QueuedPrefetcher : public BasePrefetcher
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{
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protected:
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struct DeferredPacket {
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Tick tick;
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PacketPtr pkt;
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int32_t priority;
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DeferredPacket(Tick t, PacketPtr p, int32_t pr) : tick(t), pkt(p),
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priority(pr) {}
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bool operator>(const DeferredPacket& that) const
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{
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return priority > that.priority;
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}
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bool operator<(const DeferredPacket& that) const
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{
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return priority < that.priority;
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}
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bool operator<=(const DeferredPacket& that) const
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{
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return !(*this > that);
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}
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};
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using AddrPriority = std::pair<Addr, int32_t>;
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std::list<DeferredPacket> pfq;
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// PARAMETERS
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/** Maximum size of the prefetch queue */
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const unsigned queueSize;
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/** Cycles after generation when a prefetch can first be issued */
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const Cycles latency;
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/** Squash queued prefetch if demand access observed */
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const bool queueSquash;
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/** Filter prefetches if already queued */
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const bool queueFilter;
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/** Snoop the cache before generating prefetch (cheating basically) */
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const bool cacheSnoop;
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/** Tag prefetch with PC of generating access? */
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const bool tagPrefetch;
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using const_iterator = std::list<DeferredPacket>::const_iterator;
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std::list<DeferredPacket>::const_iterator inPrefetch(Addr address,
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bool is_secure) const;
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using iterator = std::list<DeferredPacket>::iterator;
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std::list<DeferredPacket>::iterator inPrefetch(Addr address,
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bool is_secure);
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// STATS
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Stats::Scalar pfIdentified;
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Stats::Scalar pfBufferHit;
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Stats::Scalar pfInCache;
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Stats::Scalar pfRemovedFull;
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Stats::Scalar pfSpanPage;
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public:
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QueuedPrefetcher(const QueuedPrefetcherParams *p);
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virtual ~QueuedPrefetcher();
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void notify(const PacketPtr &pkt) override;
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PacketPtr insert(AddrPriority& info, bool is_secure);
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// Note: This should really be pure virtual, but doesnt go well with params
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virtual void calculatePrefetch(const PacketPtr &pkt,
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std::vector<AddrPriority> &addresses) = 0;
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PacketPtr getPacket();
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Tick nextPrefetchReadyTime() const
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{
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return pfq.empty() ? MaxTick : pfq.front().tick;
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}
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void regStats();
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};
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#endif //__MEM_CACHE_PREFETCH_QUEUED_HH__
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