8549ee4a6d
It doesn't matter if the bytes are converted before or after they're fed into the decoder. The ISA already knows what endianness to use implicitly, and this frees the CPU which doesn't from having to worry about it. Change-Id: Id6574ee81bbf4f032c1d7b2901a664f2bd014fbc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22343 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
132 lines
3.7 KiB
C++
132 lines
3.7 KiB
C++
/*
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* Copyright (c) 2012 Google
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_SPARC_DECODER_HH__
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#define __ARCH_SPARC_DECODER_HH__
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#include "arch/generic/decode_cache.hh"
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#include "arch/sparc/registers.hh"
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#include "arch/types.hh"
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#include "cpu/static_inst.hh"
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namespace SparcISA
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{
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class ISA;
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class Decoder
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{
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protected:
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// The extended machine instruction being generated
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ExtMachInst emi;
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bool instDone;
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RegVal asi;
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public:
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Decoder(ISA* isa = nullptr) : instDone(false), asi(0)
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{}
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void process() {}
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void
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reset()
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{
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instDone = false;
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}
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// Use this to give data to the predecoder. This should be used
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// when there is control flow.
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void
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moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
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{
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emi = betoh(inst);
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// The I bit, bit 13, is used to figure out where the ASI
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// should come from. Use that in the ExtMachInst. This is
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// slightly redundant, but it removes the need to put a condition
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// into all the execute functions
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if (inst & (1 << 13)) {
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emi |= (static_cast<ExtMachInst>(
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asi << (sizeof(MachInst) * 8)));
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} else {
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emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
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<< (sizeof(MachInst) * 8));
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}
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instDone = true;
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}
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bool
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needMoreBytes()
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{
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return true;
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}
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bool
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instReady()
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{
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return instDone;
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}
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void
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setContext(RegVal _asi)
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{
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asi = _asi;
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}
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void takeOverFrom(Decoder *old) {}
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protected:
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/// A cache of decoded instruction objects.
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static GenericISA::BasicDecodeCache defaultCache;
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public:
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StaticInstPtr decodeInst(ExtMachInst mach_inst);
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/// Decode a machine instruction.
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/// @param mach_inst The binary instruction to decode.
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/// @retval A pointer to the corresponding StaticInst object.
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StaticInstPtr
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decode(ExtMachInst mach_inst, Addr addr)
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{
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return defaultCache.decode(this, mach_inst, addr);
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}
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StaticInstPtr
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decode(SparcISA::PCState &nextPC)
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{
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if (!instDone)
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return NULL;
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instDone = false;
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return decode(emi, nextPC.instAddr());
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}
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};
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} // namespace SparcISA
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#endif // __ARCH_SPARC_DECODER_HH__
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