de72e36619
this patch adds an ordered response buffer to the GM pipeline to ensure in-order data delivery. the buffer is implemented as a stl ordered map, which sorts the request in program order by using their sequence ID. when requests return to the GM pipeline they are marked as done. only the oldest request may be serviced from the ordered buffer, and only if is marked as done. the FIFO response buffers are kept and used in OoO delivery mode
792 lines
23 KiB
C++
792 lines
23 KiB
C++
/*
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* Copyright (c) 2013-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Marc Orr
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*/
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#include <csignal>
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#include "arch/hsail/insts/decl.hh"
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#include "arch/hsail/insts/mem.hh"
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namespace HsailISA
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{
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// Pseudo (or magic) instructions are overloaded on the hsail call
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// instruction, because of its flexible parameter signature.
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// To add a new magic instruction:
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// 1. Add an entry to the enum.
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// 2. Implement it in the switch statement below (Call::exec).
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// 3. Add a utility function to hsa/hsail-gpu-compute/util/magicinst.h,
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// so its easy to call from an OpenCL kernel.
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// This enum should be identical to the enum in
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// hsa/hsail-gpu-compute/util/magicinst.h
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enum
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{
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MAGIC_PRINT_WF_32 = 0,
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MAGIC_PRINT_WF_64,
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MAGIC_PRINT_LANE,
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MAGIC_PRINT_LANE_64,
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MAGIC_PRINT_WF_FLOAT,
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MAGIC_SIM_BREAK,
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MAGIC_PREF_SUM,
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MAGIC_REDUCTION,
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MAGIC_MASKLANE_LOWER,
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MAGIC_MASKLANE_UPPER,
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MAGIC_JOIN_WF_BAR,
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MAGIC_WAIT_WF_BAR,
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MAGIC_PANIC,
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MAGIC_ATOMIC_NR_ADD_GLOBAL_U32_REG,
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MAGIC_ATOMIC_NR_ADD_GROUP_U32_REG,
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MAGIC_LOAD_GLOBAL_U32_REG,
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MAGIC_XACT_CAS_LD,
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MAGIC_MOST_SIG_THD,
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MAGIC_MOST_SIG_BROADCAST,
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MAGIC_PRINT_WFID_32,
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MAGIC_PRINT_WFID_64
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};
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void
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Call::execPseudoInst(Wavefront *w, GPUDynInstPtr gpuDynInst)
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{
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const VectorMask &mask = w->getPred();
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int op = 0;
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bool got_op = false;
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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int src_val0 = src1.get<int>(w, lane, 0);
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if (got_op) {
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if (src_val0 != op) {
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fatal("Multiple magic instructions per PC not "
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"supported\n");
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}
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} else {
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op = src_val0;
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got_op = true;
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}
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}
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}
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switch(op) {
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case MAGIC_PRINT_WF_32:
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MagicPrintWF32(w);
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break;
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case MAGIC_PRINT_WF_64:
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MagicPrintWF64(w);
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break;
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case MAGIC_PRINT_LANE:
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MagicPrintLane(w);
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break;
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case MAGIC_PRINT_LANE_64:
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MagicPrintLane64(w);
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break;
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case MAGIC_PRINT_WF_FLOAT:
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MagicPrintWFFloat(w);
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break;
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case MAGIC_SIM_BREAK:
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MagicSimBreak(w);
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break;
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case MAGIC_PREF_SUM:
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MagicPrefixSum(w);
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break;
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case MAGIC_REDUCTION:
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MagicReduction(w);
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break;
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case MAGIC_MASKLANE_LOWER:
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MagicMaskLower(w);
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break;
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case MAGIC_MASKLANE_UPPER:
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MagicMaskUpper(w);
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break;
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case MAGIC_JOIN_WF_BAR:
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MagicJoinWFBar(w);
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break;
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case MAGIC_WAIT_WF_BAR:
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MagicWaitWFBar(w);
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break;
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case MAGIC_PANIC:
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MagicPanic(w);
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break;
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// atomic instructions
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case MAGIC_ATOMIC_NR_ADD_GLOBAL_U32_REG:
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MagicAtomicNRAddGlobalU32Reg(w, gpuDynInst);
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break;
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case MAGIC_ATOMIC_NR_ADD_GROUP_U32_REG:
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MagicAtomicNRAddGroupU32Reg(w, gpuDynInst);
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break;
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case MAGIC_LOAD_GLOBAL_U32_REG:
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MagicLoadGlobalU32Reg(w, gpuDynInst);
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break;
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case MAGIC_XACT_CAS_LD:
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MagicXactCasLd(w);
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break;
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case MAGIC_MOST_SIG_THD:
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MagicMostSigThread(w);
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break;
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case MAGIC_MOST_SIG_BROADCAST:
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MagicMostSigBroadcast(w);
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break;
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case MAGIC_PRINT_WFID_32:
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MagicPrintWF32ID(w);
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break;
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case MAGIC_PRINT_WFID_64:
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MagicPrintWFID64(w);
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break;
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default: fatal("unrecognized magic instruction: %d\n", op);
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}
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}
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void
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Call::MagicPrintLane(Wavefront *w)
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{
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#if TRACING_ON
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const VectorMask &mask = w->getPred();
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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int src_val1 = src1.get<int>(w, lane, 1);
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int src_val2 = src1.get<int>(w, lane, 2);
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if (src_val2) {
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DPRINTFN("krl_prt (%s): CU%d, WF[%d][%d], lane %d: 0x%x\n",
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disassemble(), w->computeUnit->cu_id, w->simdId,
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w->wfSlotId, lane, src_val1);
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} else {
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DPRINTFN("krl_prt (%s): CU%d, WF[%d][%d], lane %d: %d\n",
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disassemble(), w->computeUnit->cu_id, w->simdId,
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w->wfSlotId, lane, src_val1);
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}
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}
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}
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#endif
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}
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void
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Call::MagicPrintLane64(Wavefront *w)
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{
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#if TRACING_ON
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const VectorMask &mask = w->getPred();
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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int64_t src_val1 = src1.get<int64_t>(w, lane, 1);
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int src_val2 = src1.get<int>(w, lane, 2);
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if (src_val2) {
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DPRINTFN("krl_prt (%s): CU%d, WF[%d][%d], lane %d: 0x%x\n",
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disassemble(), w->computeUnit->cu_id, w->simdId,
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w->wfSlotId, lane, src_val1);
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} else {
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DPRINTFN("krl_prt (%s): CU%d, WF[%d][%d], lane %d: %d\n",
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disassemble(), w->computeUnit->cu_id, w->simdId,
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w->wfSlotId, lane, src_val1);
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}
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}
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}
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#endif
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}
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void
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Call::MagicPrintWF32(Wavefront *w)
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{
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#if TRACING_ON
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const VectorMask &mask = w->getPred();
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std::string res_str;
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res_str = csprintf("krl_prt (%s)\n", disassemble());
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (!(lane & 7)) {
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res_str += csprintf("DB%03d: ", (int)w->wfDynId);
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}
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if (mask[lane]) {
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int src_val1 = src1.get<int>(w, lane, 1);
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int src_val2 = src1.get<int>(w, lane, 2);
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if (src_val2) {
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res_str += csprintf("%08x", src_val1);
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} else {
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res_str += csprintf("%08d", src_val1);
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}
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} else {
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res_str += csprintf("xxxxxxxx");
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}
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if ((lane & 7) == 7) {
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res_str += csprintf("\n");
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} else {
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res_str += csprintf(" ");
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}
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}
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res_str += "\n\n";
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DPRINTFN(res_str.c_str());
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#endif
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}
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void
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Call::MagicPrintWF32ID(Wavefront *w)
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{
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#if TRACING_ON
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const VectorMask &mask = w->getPred();
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std::string res_str;
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int src_val3 = -1;
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res_str = csprintf("krl_prt (%s)\n", disassemble());
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (!(lane & 7)) {
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res_str += csprintf("DB%03d: ", (int)w->wfDynId);
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}
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if (mask[lane]) {
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int src_val1 = src1.get<int>(w, lane, 1);
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int src_val2 = src1.get<int>(w, lane, 2);
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src_val3 = src1.get<int>(w, lane, 3);
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if (src_val2) {
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res_str += csprintf("%08x", src_val1);
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} else {
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res_str += csprintf("%08d", src_val1);
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}
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} else {
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res_str += csprintf("xxxxxxxx");
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}
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if ((lane & 7) == 7) {
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res_str += csprintf("\n");
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} else {
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res_str += csprintf(" ");
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}
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}
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res_str += "\n\n";
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if (w->wfDynId == src_val3) {
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DPRINTFN(res_str.c_str());
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}
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#endif
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}
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void
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Call::MagicPrintWF64(Wavefront *w)
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{
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#if TRACING_ON
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const VectorMask &mask = w->getPred();
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std::string res_str;
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res_str = csprintf("krl_prt (%s)\n", disassemble());
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (!(lane & 3)) {
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res_str += csprintf("DB%03d: ", (int)w->wfDynId);
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}
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if (mask[lane]) {
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int64_t src_val1 = src1.get<int64_t>(w, lane, 1);
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int src_val2 = src1.get<int>(w, lane, 2);
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if (src_val2) {
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res_str += csprintf("%016x", src_val1);
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} else {
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res_str += csprintf("%016d", src_val1);
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}
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} else {
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res_str += csprintf("xxxxxxxxxxxxxxxx");
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}
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if ((lane & 3) == 3) {
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res_str += csprintf("\n");
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} else {
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res_str += csprintf(" ");
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}
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}
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res_str += "\n\n";
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DPRINTFN(res_str.c_str());
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#endif
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}
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void
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Call::MagicPrintWFID64(Wavefront *w)
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{
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#if TRACING_ON
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const VectorMask &mask = w->getPred();
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std::string res_str;
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int src_val3 = -1;
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res_str = csprintf("krl_prt (%s)\n", disassemble());
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (!(lane & 3)) {
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res_str += csprintf("DB%03d: ", (int)w->wfDynId);
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}
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if (mask[lane]) {
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int64_t src_val1 = src1.get<int64_t>(w, lane, 1);
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int src_val2 = src1.get<int>(w, lane, 2);
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src_val3 = src1.get<int>(w, lane, 3);
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if (src_val2) {
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res_str += csprintf("%016x", src_val1);
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} else {
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res_str += csprintf("%016d", src_val1);
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}
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} else {
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res_str += csprintf("xxxxxxxxxxxxxxxx");
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}
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if ((lane & 3) == 3) {
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res_str += csprintf("\n");
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} else {
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res_str += csprintf(" ");
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}
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}
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res_str += "\n\n";
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if (w->wfDynId == src_val3) {
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DPRINTFN(res_str.c_str());
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}
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#endif
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}
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void
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Call::MagicPrintWFFloat(Wavefront *w)
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{
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#if TRACING_ON
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const VectorMask &mask = w->getPred();
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std::string res_str;
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res_str = csprintf("krl_prt (%s)\n", disassemble());
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (!(lane & 7)) {
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res_str += csprintf("DB%03d: ", (int)w->wfDynId);
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}
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if (mask[lane]) {
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float src_val1 = src1.get<float>(w, lane, 1);
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res_str += csprintf("%08f", src_val1);
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} else {
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res_str += csprintf("xxxxxxxx");
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}
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if ((lane & 7) == 7) {
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res_str += csprintf("\n");
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} else {
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res_str += csprintf(" ");
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}
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}
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res_str += "\n\n";
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DPRINTFN(res_str.c_str());
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#endif
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}
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// raises a signal that GDB will catch
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// when done with the break, type "signal 0" in gdb to continue
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void
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Call::MagicSimBreak(Wavefront *w)
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{
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std::string res_str;
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// print out state for this wavefront and then break
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res_str = csprintf("Breakpoint encountered for wavefront %i\n",
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w->wfSlotId);
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res_str += csprintf(" Kern ID: %i\n", w->kernId);
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res_str += csprintf(" Phase ID: %i\n", w->simdId);
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res_str += csprintf(" Executing on CU #%i\n", w->computeUnit->cu_id);
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res_str += csprintf(" Exec mask: ");
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for (int i = w->computeUnit->wfSize() - 1; i >= 0; --i) {
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if (w->execMask(i))
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res_str += "1";
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else
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res_str += "0";
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if ((i & 7) == 7)
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res_str += " ";
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}
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res_str += csprintf("(0x%016llx)\n", w->execMask().to_ullong());
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res_str += "\nHelpful debugging hints:\n";
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res_str += " Check out w->s_reg / w->d_reg for register state\n";
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res_str += "\n\n";
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DPRINTFN(res_str.c_str());
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fflush(stdout);
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raise(SIGTRAP);
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}
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void
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Call::MagicPrefixSum(Wavefront *w)
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{
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const VectorMask &mask = w->getPred();
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int res = 0;
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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int src_val1 = src1.get<int>(w, lane, 1);
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dest.set<int>(w, lane, res);
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res += src_val1;
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}
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}
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}
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void
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Call::MagicReduction(Wavefront *w)
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{
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// reduction magic instruction
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// The reduction instruction takes up to 64 inputs (one from
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// each thread in a WF) and sums them. It returns the sum to
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// each thread in the WF.
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const VectorMask &mask = w->getPred();
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int res = 0;
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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int src_val1 = src1.get<int>(w, lane, 1);
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res += src_val1;
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}
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}
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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dest.set<int>(w, lane, res);
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}
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}
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}
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void
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Call::MagicMaskLower(Wavefront *w)
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{
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const VectorMask &mask = w->getPred();
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int res = 0;
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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int src_val1 = src1.get<int>(w, lane, 1);
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if (src_val1) {
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if (lane < (w->computeUnit->wfSize()/2)) {
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res = res | ((uint32_t)(1) << lane);
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}
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}
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}
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}
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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dest.set<int>(w, lane, res);
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}
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}
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}
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void
|
|
Call::MagicMaskUpper(Wavefront *w)
|
|
{
|
|
const VectorMask &mask = w->getPred();
|
|
int res = 0;
|
|
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
|
|
if (mask[lane]) {
|
|
int src_val1 = src1.get<int>(w, lane, 1);
|
|
|
|
if (src_val1) {
|
|
if (lane >= (w->computeUnit->wfSize()/2)) {
|
|
res = res | ((uint32_t)(1) <<
|
|
(lane - (w->computeUnit->wfSize()/2)));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
|
|
if (mask[lane]) {
|
|
dest.set<int>(w, lane, res);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
Call::MagicJoinWFBar(Wavefront *w)
|
|
{
|
|
const VectorMask &mask = w->getPred();
|
|
int max_cnt = 0;
|
|
|
|
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
|
|
if (mask[lane]) {
|
|
w->barCnt[lane]++;
|
|
|
|
if (w->barCnt[lane] > max_cnt) {
|
|
max_cnt = w->barCnt[lane];
|
|
}
|
|
}
|
|
}
|
|
|
|
if (max_cnt > w->maxBarCnt) {
|
|
w->maxBarCnt = max_cnt;
|
|
}
|
|
}
|
|
|
|
void
|
|
Call::MagicWaitWFBar(Wavefront *w)
|
|
{
|
|
const VectorMask &mask = w->getPred();
|
|
int max_cnt = 0;
|
|
|
|
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
|
|
if (mask[lane]) {
|
|
w->barCnt[lane]--;
|
|
}
|
|
|
|
if (w->barCnt[lane] > max_cnt) {
|
|
max_cnt = w->barCnt[lane];
|
|
}
|
|
}
|
|
|
|
if (max_cnt < w->maxBarCnt) {
|
|
w->maxBarCnt = max_cnt;
|
|
}
|
|
|
|
w->instructionBuffer.erase(w->instructionBuffer.begin() + 1,
|
|
w->instructionBuffer.end());
|
|
if (w->pendingFetch)
|
|
w->dropFetch = true;
|
|
}
|
|
|
|
void
|
|
Call::MagicPanic(Wavefront *w)
|
|
{
|
|
const VectorMask &mask = w->getPred();
|
|
|
|
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
|
|
if (mask[lane]) {
|
|
int src_val1 = src1.get<int>(w, lane, 1);
|
|
panic("OpenCL Code failed assertion #%d. Triggered by lane %s",
|
|
src_val1, lane);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
Call::calcAddr(Wavefront *w, GPUDynInstPtr m)
|
|
{
|
|
// the address is in src1 | src2
|
|
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
|
|
int src_val1 = src1.get<int>(w, lane, 1);
|
|
int src_val2 = src1.get<int>(w, lane, 2);
|
|
Addr addr = (((Addr) src_val1) << 32) | ((Addr) src_val2);
|
|
|
|
m->addr[lane] = addr;
|
|
}
|
|
|
|
}
|
|
|
|
void
|
|
Call::MagicAtomicNRAddGlobalU32Reg(Wavefront *w, GPUDynInstPtr gpuDynInst)
|
|
{
|
|
GPUDynInstPtr m = gpuDynInst;
|
|
|
|
calcAddr(w, m);
|
|
|
|
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
|
|
((int*)m->a_data)[lane] = src1.get<int>(w, lane, 3);
|
|
}
|
|
|
|
setFlag(AtomicNoReturn);
|
|
setFlag(AtomicAdd);
|
|
setFlag(NoScope);
|
|
setFlag(NoOrder);
|
|
setFlag(GlobalSegment);
|
|
|
|
m->m_type = U32::memType;
|
|
m->v_type = U32::vgprType;
|
|
|
|
m->exec_mask = w->execMask();
|
|
m->statusBitVector = 0;
|
|
m->equiv = 0; // atomics don't have an equivalence class operand
|
|
m->n_reg = 1;
|
|
|
|
m->simdId = w->simdId;
|
|
m->wfSlotId = w->wfSlotId;
|
|
m->wfDynId = w->wfDynId;
|
|
m->latency.init(&w->computeUnit->shader->tick_cnt);
|
|
|
|
m->pipeId = GLBMEM_PIPE;
|
|
m->latency.set(w->computeUnit->shader->ticks(64));
|
|
w->computeUnit->globalMemoryPipe.issueRequest(m);
|
|
w->outstandingReqsWrGm++;
|
|
w->wrGmReqsInPipe--;
|
|
w->outstandingReqsRdGm++;
|
|
w->rdGmReqsInPipe--;
|
|
w->outstandingReqs++;
|
|
w->memReqsInPipe--;
|
|
}
|
|
|
|
void
|
|
Call::MagicAtomicNRAddGroupU32Reg(Wavefront *w, GPUDynInstPtr gpuDynInst)
|
|
{
|
|
GPUDynInstPtr m = gpuDynInst;
|
|
calcAddr(w, m);
|
|
|
|
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
|
|
((int*)m->a_data)[lane] = src1.get<int>(w, lane, 1);
|
|
}
|
|
|
|
setFlag(AtomicNoReturn);
|
|
setFlag(AtomicAdd);
|
|
setFlag(NoScope);
|
|
setFlag(NoOrder);
|
|
setFlag(GlobalSegment);
|
|
|
|
m->m_type = U32::memType;
|
|
m->v_type = U32::vgprType;
|
|
|
|
m->exec_mask = w->execMask();
|
|
m->statusBitVector = 0;
|
|
m->equiv = 0; // atomics don't have an equivalence class operand
|
|
m->n_reg = 1;
|
|
|
|
m->simdId = w->simdId;
|
|
m->wfSlotId = w->wfSlotId;
|
|
m->wfDynId = w->wfDynId;
|
|
m->latency.init(&w->computeUnit->shader->tick_cnt);
|
|
|
|
m->pipeId = GLBMEM_PIPE;
|
|
m->latency.set(w->computeUnit->shader->ticks(64));
|
|
w->computeUnit->globalMemoryPipe.issueRequest(m);
|
|
w->outstandingReqsWrGm++;
|
|
w->wrGmReqsInPipe--;
|
|
w->outstandingReqsRdGm++;
|
|
w->rdGmReqsInPipe--;
|
|
w->outstandingReqs++;
|
|
w->memReqsInPipe--;
|
|
}
|
|
|
|
void
|
|
Call::MagicLoadGlobalU32Reg(Wavefront *w, GPUDynInstPtr gpuDynInst)
|
|
{
|
|
GPUDynInstPtr m = gpuDynInst;
|
|
// calculate the address
|
|
calcAddr(w, m);
|
|
|
|
setFlag(Load);
|
|
setFlag(NoScope);
|
|
setFlag(NoOrder);
|
|
setFlag(GlobalSegment);
|
|
|
|
m->m_type = U32::memType; //MemDataType::memType;
|
|
m->v_type = U32::vgprType; //DestDataType::vgprType;
|
|
|
|
m->exec_mask = w->execMask();
|
|
m->statusBitVector = 0;
|
|
m->equiv = 0;
|
|
m->n_reg = 1;
|
|
|
|
// FIXME
|
|
//m->dst_reg = this->dest.regIndex();
|
|
|
|
m->simdId = w->simdId;
|
|
m->wfSlotId = w->wfSlotId;
|
|
m->wfDynId = w->wfDynId;
|
|
m->latency.init(&w->computeUnit->shader->tick_cnt);
|
|
|
|
m->pipeId = GLBMEM_PIPE;
|
|
m->latency.set(w->computeUnit->shader->ticks(1));
|
|
w->computeUnit->globalMemoryPipe.issueRequest(m);
|
|
w->outstandingReqsRdGm++;
|
|
w->rdGmReqsInPipe--;
|
|
w->outstandingReqs++;
|
|
w->memReqsInPipe--;
|
|
}
|
|
|
|
void
|
|
Call::MagicXactCasLd(Wavefront *w)
|
|
{
|
|
const VectorMask &mask = w->getPred();
|
|
int src_val1 = 0;
|
|
|
|
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
|
|
if (mask[lane]) {
|
|
src_val1 = src1.get<int>(w, lane, 1);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!w->computeUnit->xactCasLoadMap.count(src_val1)) {
|
|
w->computeUnit->xactCasLoadMap[src_val1] = ComputeUnit::waveQueue();
|
|
w->computeUnit->xactCasLoadMap[src_val1].waveIDQueue.clear();
|
|
}
|
|
|
|
w->computeUnit->xactCasLoadMap[src_val1].waveIDQueue
|
|
.push_back(ComputeUnit::waveIdentifier(w->simdId, w->wfSlotId));
|
|
}
|
|
|
|
void
|
|
Call::MagicMostSigThread(Wavefront *w)
|
|
{
|
|
const VectorMask &mask = w->getPred();
|
|
unsigned mst = true;
|
|
|
|
for (int lane = w->computeUnit->wfSize() - 1; lane >= 0; --lane) {
|
|
if (mask[lane]) {
|
|
dest.set<int>(w, lane, mst);
|
|
mst = false;
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
Call::MagicMostSigBroadcast(Wavefront *w)
|
|
{
|
|
const VectorMask &mask = w->getPred();
|
|
int res = 0;
|
|
bool got_res = false;
|
|
|
|
for (int lane = w->computeUnit->wfSize() - 1; lane >= 0; --lane) {
|
|
if (mask[lane]) {
|
|
if (!got_res) {
|
|
res = src1.get<int>(w, lane, 1);
|
|
got_res = true;
|
|
}
|
|
dest.set<int>(w, lane, res);
|
|
}
|
|
}
|
|
}
|
|
|
|
} // namespace HsailISA
|