configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore
--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
141 lines
3.6 KiB
C++
141 lines
3.6 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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*/
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#ifndef __BASE_BITFIELD_HH__
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#define __BASE_BITFIELD_HH__
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#include <inttypes.h>
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/**
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* Generate a 64-bit mask of 'nbits' 1s, right justified.
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*/
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inline uint64_t
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mask(int nbits)
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{
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return (nbits == 64) ? (uint64_t)-1LL : (1ULL << nbits) - 1;
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}
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/**
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* Extract the bitfield from position 'first' to 'last' (inclusive)
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* from 'val' and right justify it. MSB is numbered 63, LSB is 0.
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*/
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template <class T>
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inline
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T
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bits(T val, int first, int last)
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{
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int nbits = first - last + 1;
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return (val >> last) & mask(nbits);
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}
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/**
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* Mask off the given bits in place like bits() but without shifting.
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* msb = 63, lsb = 0
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*/
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template <class T>
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inline
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T
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mbits(T val, int first, int last)
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{
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return val & (mask(first+1) & ~mask(last));
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}
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inline uint64_t
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mask(int first, int last)
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{
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return mbits((uint64_t)-1LL, first, last);
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}
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/**
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* Sign-extend an N-bit value to 64 bits.
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*/
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template <int N>
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inline
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int64_t
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sext(uint64_t val)
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{
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int sign_bit = bits(val, N-1, N-1);
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return sign_bit ? (val | ~mask(N)) : val;
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}
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/**
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* Return val with bits first to last set to bit_val
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*/
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template <class T, class B>
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inline
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T
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insertBits(T val, int first, int last, B bit_val)
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{
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T bmask = mask(first - last + 1) << last;
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return ((bit_val << last) & bmask) | (val & ~bmask);
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}
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/**
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* A convenience function to replace bits first to last of val with bit_val
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* in place.
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*/
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template <class T, class B>
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inline
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void
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replaceBits(T& val, int first, int last, B bit_val)
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{
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val = insertBits(val, first, last, bit_val);
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}
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/**
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* Returns the bit position of the MSB that is set in the input
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*/
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inline
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int
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findMsbSet(uint64_t val) {
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int msb = 0;
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if (!val)
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return 0;
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if (bits(val, 63,32)) msb += 32;
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val >>= 32;
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if (bits(val, 31,16)) msb += 16;
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val >>= 16;
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if (bits(val, 15,8)) msb += 8;
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val >>= 8;
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if (bits(val, 7,4)) msb += 4;
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val >>= 4;
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if (bits(val, 3,2)) msb += 2;
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val >>= 2;
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if (bits(val, 1,1)) msb += 1;
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return msb;
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}
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#endif // __BASE_BITFIELD_HH__
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