Giacomo Travaglini 81a3637260 arch-x86: Add byteEnable mask in x86 memhelpers ...

Next patch will make the byteEnable mandatory in the ExecContext
interface so we need to amend the existing helpers to make them
use generate the boolean vector.

JIRA: https://gem5.atlassian.net/browse/GEM5-196

Change-Id: Ib24550aa1e22049487ef4ec2748b786be456d342
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23529
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

2020-09-30 08:50:39 +00:00

..

arm

arch-arm: Using new "raw" memhelpers

2020-09-30 08:50:39 +00:00

gcn3

gpu-compute: set exec_mask for permute,bpermute instructions

2020-09-24 17:56:04 +00:00

generic

arch: Add raw read/writeMem helpers

2020-09-30 08:50:39 +00:00

mips

misc: Update attribute syntax, and reorganize compiler.hh.

2020-09-28 21:52:59 +00:00

null

base, sim, mem, arch: Remove the dummy CPU in NULL

2020-09-14 08:52:40 +00:00

power

misc: Update attribute syntax, and reorganize compiler.hh.

2020-09-28 21:52:59 +00:00

riscv

misc: Update attribute syntax, and reorganize compiler.hh.

2020-09-28 21:52:59 +00:00

sparc

misc: Update attribute syntax, and reorganize compiler.hh.

2020-09-28 21:52:59 +00:00

x86

arch-x86: Add byteEnable mask in x86 memhelpers

2020-09-30 08:50:39 +00:00

isa_parser.py

arch: Do value-initialization for MemOperand

2020-09-30 08:50:39 +00:00

micro_asm_test.py

arch: Delete authors lists from generic arch files.

2020-02-18 03:34:56 +00:00

micro_asm.py

misc: Make exception handling python3 compliant

2020-03-13 14:24:07 +00:00

SConscript

arch,cpu,sim: Get rid of the microcode ROM stub code.

2020-08-25 12:41:30 +00:00