Joel Hestness 234fa4cf7e Standard Switch: Drain the system before switching CPUs ...

When switching from an atomic CPU to any of the timing CPUs, a drain is
unnecessary since no events are scheduled in atomic mode. However, when
trying to switch CPUs starting with a timing CPU, there may be events
scheduled. This change ensures that all events are drained from the system
by calling m5.drain before switching CPUs.

2012-09-12 21:41:37 -05:00

..

Benchmarks.py

configs: add run scripts for ics/gb versions of android and bbench

2012-06-11 11:07:42 -04:00

CacheConfig.py

Bus: Split the bus into a non-coherent and coherent bus

2012-05-31 13:30:04 -04:00

Caches.py

O3: Remove hardcoded tgts_per_mshr in O3CPU.py.

2011-12-01 00:15:22 -08:00

cpu2000.py

cpu2000: Add missing art benchmark to all

2012-01-09 18:08:20 -06:00

FSConfig.py

Bridge: Remove NACKs in the bridge and unify with packet queue

2012-08-22 11:39:58 -04:00

O3_ARM_v7a.py

prefetcher: Make prefetcher a sim object instead of it being a parameter on cache

2012-02-12 16:07:38 -06:00

Options.py

se.py: support specifying multiple programs via command line

2012-09-09 09:33:45 -05:00

Simulation.py

Standard Switch: Drain the system before switching CPUs

2012-09-12 21:41:37 -05:00

SysPaths.py

make rcS files read from the m5 source directory, not /dist.

2006-11-08 14:10:25 -05:00