15adefd7bc
This change adds support for HSA devices, which are DMA devices that have an HSA packet processor (HSAPP). An HSA packet processor model is also included. The HSAPP is a DMA device that matains AQL packet queues and handles extraction of AQL packets, scheduling of AQL queues, and initiates kernel launch for HSA devices. Because these devices directly interact with low-level software and aid in the implementation of the HSA ABI we also include some headers from the ROCm runtime: the hsa.h and kfd_ioctl.h headers. These aid with support ROCm for the HSA devices and drivers. Change-Id: I24305e0337edc6fa555d436697b4e607a1e097d5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28128 Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
118 lines
3.5 KiB
Plaintext
118 lines
3.5 KiB
Plaintext
See CONTRIBUTING.md for details of gem5's contribution process.
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This file contains the keywords used in commit messages. Each keyword has one
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or more maintainers. At least one (not all) of these maintainers must review
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the patch before it can be pushed. These people will automatically be emailed
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when you upload the patch to Gerrit (https://gem5-review.googlesource.com).
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These keywords mostly follow the directory structure.
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Individuals on the project management committee are maintainers for all of the
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gem5 components (i.e., they can review any patch as the maintainer). These
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individuals are required to review any patches to components without explicit
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maintainers.
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PMC Members (general maintainers):
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Ali Saidi <asaidi@gmail.com>
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Andreas Sandberg <andreas.sandberg@arm.com>
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Brad Beckmann <brad.beckmann@amd.com>
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David Wood <david@cs.wisc.edu>
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Gabe Black <gabeblack@google.com>
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Giacomo Travaglini <giacomo.travaglini@arm.com>
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Jason Lowe-Power <jason@lowepower.com> (chair)
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Matt Sinclair <sinclair@cs.wisc.edu>
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Tony Gutierrez <anthony.gutierrez@amd.com>
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Steve Reinhardt <stever@gmail.com>
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arch: General architecture-specific components
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Gabe Black <gabeblack@google.com>
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arch-arm:
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Andreas Sandberg <andreas.sandberg@arm.com>
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Giacomo Travaglini <giacomo.travaglini@arm.com>
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arch-gcn3:
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arch-hsail:
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Tony Gutierrez <anthony.gutierrez@amd.com>
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arch-mips:
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arch-power:
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arch-riscv:
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Alec Roelke <ar4jc@virginia.edu>
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arch-sparc:
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Gabe Black <gabeblack@google.com>
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arch-x86:
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Gabe Black <gabeblack@google.com>
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base:
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configs:
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Jason Lowe-Power <jason@lowepower.com>
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cpu: General changes to all CPU models (e.g., BaseCPU)
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cpu-kvm:
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Andreas Sandberg <andreas.sandberg@arm.com>
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cpu-minor:
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cpu-o3:
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cpu-simple:
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dev:
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dev-hsa:
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Tony Gutierrez <anthony.gutierrez@amd.com>
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dev-virtio:
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Andreas Sandberg <andreas.sandberg@arm.com>
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dev-arm:
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Andreas Sandberg <andreas.sandberg@arm.com>
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Giacomo Travaglini <giacomo.travaglini@arm.com>
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ext: Components external to gem5
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fastmodel: Changes relating to ARM Fast Models
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Gabe Black <gabeblack@google.com>
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gpu-compute:
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Tony Gutierrez <anthony.gutierrez@amd.com>
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learning-gem5: The code and configs for the Learning gem5 book (see
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learning.gem5.com)
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Jason Lowe-Power <jason@lowepower.com>
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mem: General memory system (e.g., XBar, Packet)
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Nikos Nikoleris <nikos.nikoleris@arm.com>
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mem-cache: Classic caches and coherence
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Nikos Nikoleris <nikos.nikoleris@arm.com>
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mem-garnet: Garnet subcomponent of Ruby
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Tushar Krishna <tushar@ece.gatech.edu>
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mem-ruby: Ruby structures and protocols
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Brad Beckmann <brad.beckmann@amd.com>
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Jason Lowe-Power <jason@lowepower.com>
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misc: Anything outside of the other categories
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python: Python SimObject wrapping and infrastructure
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Andreas Sandberg <andreas.sandberg@arm.com>
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scons: Build system
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Gabe Black <gabeblack@google.com>
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sim: General simulation components
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Jason Lowe-Power <jason@lowepower.com>
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sim-se: Syscall emulation
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Brandon Potter <brandon.potter@amd.com>
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sim-power: Power modeling
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Andreas Sandberg <andreas.sandberg@arm.com>
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stats: Updates to statistics for regressions
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system: System boot code and related components
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system-alpha:
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system-arm:
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Andreas Sandberg <andreas.sandberg@arm.com>
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Giacomo Travaglini <giacomo.travaglini@arm.com>
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systemc: Code for the gem5 SystemC implementation and interface
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Gabe Black <gabeblack@google.com>
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tests: testing changes (not stats updates for tests. See stats:)
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Bobby Bruce <bbruce@ucdavis.edu>
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util:
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Gabe Black <gabeblack@google.com>
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