7e84a14a26
Adds support for profiling "unaddressed" transactions, which are associated with a unique ID rather than a memory address, to AbstractController. JIRA: https://gem5.atlassian.net/browse/GEM5-1097 Change-Id: Ib75f3f38dc4910acc2ad4f1c7bf88c9193568203 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57297 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
448 lines
17 KiB
C++
448 lines
17 KiB
C++
/*
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* Copyright (c) 2017,2019-2021 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009-2014 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
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#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
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#include <exception>
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#include <iostream>
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#include <string>
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#include <unordered_map>
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#include "base/addr_range.hh"
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#include "base/addr_range_map.hh"
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#include "base/callback.hh"
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#include "mem/packet.hh"
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#include "mem/qport.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/ruby/common/DataBlock.hh"
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#include "mem/ruby/common/Histogram.hh"
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#include "mem/ruby/common/MachineID.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/protocol/AccessPermission.hh"
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#include "mem/ruby/system/CacheRecorder.hh"
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#include "params/RubyController.hh"
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#include "sim/clocked_object.hh"
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namespace gem5
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{
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namespace ruby
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{
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class Network;
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class GPUCoalescer;
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class DMASequencer;
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// used to communicate that an in_port peeked the wrong message type
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class RejectException: public std::exception
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{
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virtual const char* what() const throw()
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{ return "Port rejected message based on type"; }
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};
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class AbstractController : public ClockedObject, public Consumer
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{
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public:
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PARAMS(RubyController);
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AbstractController(const Params &p);
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void init();
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NodeID getVersion() const { return m_machineID.getNum(); }
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MachineType getType() const { return m_machineID.getType(); }
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void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
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// return instance name
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void blockOnQueue(Addr, MessageBuffer*);
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bool isBlocked(Addr) const;
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void unblock(Addr);
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bool isBlocked(Addr);
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virtual MessageBuffer* getMandatoryQueue() const = 0;
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virtual MessageBuffer* getMemReqQueue() const = 0;
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virtual MessageBuffer* getMemRespQueue() const = 0;
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virtual AccessPermission getAccessPermission(const Addr &addr) = 0;
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virtual void print(std::ostream & out) const = 0;
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virtual void wakeup() = 0;
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virtual void resetStats() = 0;
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virtual void regStats();
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virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
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virtual Sequencer* getCPUSequencer() const = 0;
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virtual DMASequencer* getDMASequencer() const = 0;
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virtual GPUCoalescer* getGPUCoalescer() const = 0;
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// This latency is used by the sequencer when enqueueing requests.
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// Different latencies may be used depending on the request type.
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// This is the hit latency unless the top-level cache controller
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// introduces additional cycles in the response path.
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virtual Cycles mandatoryQueueLatency(const RubyRequestType& param_type)
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{ return m_mandatory_queue_latency; }
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//! These functions are used by ruby system to read/write the data blocks
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//! that exist with in the controller.
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virtual bool functionalReadBuffers(PacketPtr&) = 0;
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virtual void functionalRead(const Addr &addr, PacketPtr)
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{ panic("functionalRead(Addr,PacketPtr) not implemented"); }
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//! Functional read that reads only blocks not present in the mask.
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//! Return number of bytes read.
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virtual bool functionalReadBuffers(PacketPtr&, WriteMask &mask) = 0;
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virtual void functionalRead(const Addr &addr, PacketPtr pkt,
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WriteMask &mask)
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{ panic("functionalRead(Addr,PacketPtr,WriteMask) not implemented"); }
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void functionalMemoryRead(PacketPtr);
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//! The return value indicates the number of messages written with the
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//! data from the packet.
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virtual int functionalWriteBuffers(PacketPtr&) = 0;
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virtual int functionalWrite(const Addr &addr, PacketPtr) = 0;
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int functionalMemoryWrite(PacketPtr);
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//! Function for enqueuing a prefetch request
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virtual void enqueuePrefetch(const Addr &, const RubyRequestType&)
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{ fatal("Prefetches not implemented!");}
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//! Notifies controller of a request coalesced at the sequencer.
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//! By default, it does nothing. Behavior is protocol-specific
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virtual void notifyCoalesced(const Addr& addr,
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const RubyRequestType& type,
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const RequestPtr& req,
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const DataBlock& data_blk,
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const bool& was_miss)
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{ }
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//! Function for collating statistics from all the controllers of this
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//! particular type. This function should only be called from the
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//! version 0 of this controller type.
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virtual void collateStats()
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{fatal("collateStats() should be overridden!");}
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//! Initialize the message buffers.
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virtual void initNetQueues() = 0;
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/** A function used to return the port associated with this bus object. */
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Port &getPort(const std::string &if_name,
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PortID idx=InvalidPortID);
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void recvTimingResp(PacketPtr pkt);
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Tick recvAtomic(PacketPtr pkt);
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const AddrRangeList &getAddrRanges() const { return addrRanges; }
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public:
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MachineID getMachineID() const { return m_machineID; }
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RequestorID getRequestorId() const { return m_id; }
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statistics::Histogram& getDelayHist() { return stats.delayHistogram; }
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statistics::Histogram& getDelayVCHist(uint32_t index)
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{ return *(stats.delayVCHistogram[index]); }
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bool respondsTo(Addr addr)
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{
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for (auto &range: addrRanges)
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if (range.contains(addr)) return true;
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return false;
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}
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/**
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* Map an address to the correct MachineID
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*
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* This function querries the network for the NodeID of the
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* destination for a given request using its address and the type
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* of the destination. For example for a request with a given
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* address to a directory it will return the MachineID of the
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* authorative directory.
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*
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* @param the destination address
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* @param the type of the destination
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* @return the MachineID of the destination
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*/
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MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
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/**
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* Maps an address to the correct dowstream MachineID (i.e. the component
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* in the next level of the cache hierarchy towards memory)
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*
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* This function uses the local list of possible destinations instead of
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* querying the network.
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*
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* @param the destination address
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* @param the type of the destination (optional)
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* @return the MachineID of the destination
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*/
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MachineID mapAddressToDownstreamMachine(Addr addr,
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MachineType mtype = MachineType_NUM) const;
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/** List of downstream destinations (towards memory) */
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const NetDest& allDownstreamDest() const { return downstreamDestinations; }
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/** List of upstream destinations (towards the CPU) */
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const NetDest& allUpstreamDest() const { return upstreamDestinations; }
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protected:
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//! Profiles original cache requests including PUTs
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void profileRequest(const std::string &request);
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//! Profiles the delay associated with messages.
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void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
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// Tracks outstanding transactions for latency profiling
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struct TransMapPair { unsigned transaction; unsigned state; Tick time; };
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std::unordered_map<Addr, TransMapPair> m_inTransAddressed;
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std::unordered_map<Addr, TransMapPair> m_outTransAddressed;
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std::unordered_map<Addr, TransMapPair> m_inTransUnaddressed;
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std::unordered_map<Addr, TransMapPair> m_outTransUnaddressed;
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/**
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* Profiles an event that initiates a protocol transactions for a specific
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* line (e.g. events triggered by incoming request messages).
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* A histogram with the latency of the transactions is generated for
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* all combinations of trigger event, initial state, and final state.
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* This function also supports "unaddressed" transactions,
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* those not associated with an address in memory but
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* instead associated with a unique ID.
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*
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* @param addr address of the line, or unique transaction ID
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* @param type event that started the transaction
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* @param initialState state of the line before the transaction
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* @param isAddressed is addr a line address or a unique ID
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*/
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template<typename EventType, typename StateType>
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void incomingTransactionStart(Addr addr,
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EventType type, StateType initialState, bool retried,
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bool isAddressed=true)
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{
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auto& m_inTrans =
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isAddressed ? m_inTransAddressed : m_inTransUnaddressed;
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assert(m_inTrans.find(addr) == m_inTrans.end());
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m_inTrans[addr] = {type, initialState, curTick()};
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if (retried)
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++(*stats.inTransLatRetries[type]);
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}
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/**
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* Profiles an event that ends a transaction.
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* This function also supports "unaddressed" transactions,
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* those not associated with an address in memory but
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* instead associated with a unique ID.
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*
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* @param addr address or unique ID with an outstanding transaction
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* @param finalState state of the line after the transaction
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* @param isAddressed is addr a line address or a unique ID
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*/
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template<typename StateType>
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void incomingTransactionEnd(Addr addr, StateType finalState,
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bool isAddressed=true)
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{
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auto& m_inTrans =
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isAddressed ? m_inTransAddressed : m_inTransUnaddressed;
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auto iter = m_inTrans.find(addr);
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assert(iter != m_inTrans.end());
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stats.inTransLatHist[iter->second.transaction]
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[iter->second.state]
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[(unsigned)finalState]->sample(
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ticksToCycles(curTick() - iter->second.time));
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++(*stats.inTransLatTotal[iter->second.transaction]);
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m_inTrans.erase(iter);
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}
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/**
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* Profiles an event that initiates a transaction in a peer controller
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* (e.g. an event that sends a request message)
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* This function also supports "unaddressed" transactions,
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* those not associated with an address in memory but
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* instead associated with a unique ID.
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*
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* @param addr address of the line or a unique transaction ID
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* @param type event that started the transaction
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* @param isAddressed is addr a line address or a unique ID
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*/
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template<typename EventType>
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void outgoingTransactionStart(Addr addr, EventType type,
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bool isAddressed=true)
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{
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auto& m_outTrans =
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isAddressed ? m_outTransAddressed : m_outTransUnaddressed;
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assert(m_outTrans.find(addr) == m_outTrans.end());
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m_outTrans[addr] = {type, 0, curTick()};
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}
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/**
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* Profiles the end of an outgoing transaction.
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* (e.g. receiving the response for a requests)
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* This function also supports "unaddressed" transactions,
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* those not associated with an address in memory but
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* instead associated with a unique ID.
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*
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* @param addr address of the line with an outstanding transaction
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* @param isAddressed is addr a line address or a unique ID
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*/
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void outgoingTransactionEnd(Addr addr, bool retried,
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bool isAddressed=true)
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{
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auto& m_outTrans =
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isAddressed ? m_outTransAddressed : m_outTransUnaddressed;
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auto iter = m_outTrans.find(addr);
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assert(iter != m_outTrans.end());
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stats.outTransLatHist[iter->second.transaction]->sample(
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ticksToCycles(curTick() - iter->second.time));
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if (retried)
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++(*stats.outTransLatHistRetries[iter->second.transaction]);
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m_outTrans.erase(iter);
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}
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void stallBuffer(MessageBuffer* buf, Addr addr);
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void wakeUpBuffer(MessageBuffer* buf, Addr addr);
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void wakeUpBuffers(Addr addr);
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void wakeUpAllBuffers(Addr addr);
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void wakeUpAllBuffers();
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bool serviceMemoryQueue();
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protected:
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const NodeID m_version;
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MachineID m_machineID;
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const NodeID m_clusterID;
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// RequestorID used by some components of gem5.
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const RequestorID m_id;
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Network *m_net_ptr;
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bool m_is_blocking;
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std::map<Addr, MessageBuffer*> m_block_map;
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typedef std::vector<MessageBuffer*> MsgVecType;
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typedef std::set<MessageBuffer*> MsgBufType;
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typedef std::map<Addr, MsgVecType* > WaitingBufType;
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WaitingBufType m_waiting_buffers;
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unsigned int m_in_ports;
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unsigned int m_cur_in_port;
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const int m_number_of_TBEs;
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const int m_transitions_per_cycle;
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const unsigned int m_buffer_size;
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Cycles m_recycle_latency;
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const Cycles m_mandatory_queue_latency;
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bool m_waiting_mem_retry;
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/**
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* Port that forwards requests and receives responses from the
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* memory controller.
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*/
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class MemoryPort : public RequestPort
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{
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private:
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// Controller that operates this port.
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AbstractController *controller;
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public:
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MemoryPort(const std::string &_name, AbstractController *_controller,
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PortID id = InvalidPortID);
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protected:
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// Function for receiving a timing response from the peer port.
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// Currently the pkt is handed to the coherence controller
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// associated with this port.
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bool recvTimingResp(PacketPtr pkt);
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void recvReqRetry();
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};
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/* Request port to the memory controller. */
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MemoryPort memoryPort;
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// State that is stored in packets sent to the memory controller.
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struct SenderState : public Packet::SenderState
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{
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// Id of the machine from which the request originated.
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MachineID id;
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SenderState(MachineID _id) : id(_id)
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{}
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};
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private:
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/** The address range to which the controller responds on the CPU side. */
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const AddrRangeList addrRanges;
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typedef std::unordered_map<MachineType, MachineID> AddrMapEntry;
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AddrRangeMap<AddrMapEntry, 3> downstreamAddrMap;
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NetDest downstreamDestinations;
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NetDest upstreamDestinations;
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public:
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struct ControllerStats : public statistics::Group
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{
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ControllerStats(statistics::Group *parent);
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// Initialized by the SLICC compiler for all combinations of event and
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// states. Only histograms with samples will appear in the stats
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std::vector<std::vector<std::vector<statistics::Histogram*>>>
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inTransLatHist;
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std::vector<statistics::Scalar*> inTransLatRetries;
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std::vector<statistics::Scalar*> inTransLatTotal;
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// Initialized by the SLICC compiler for all events.
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// Only histograms with samples will appear in the stats.
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std::vector<statistics::Histogram*> outTransLatHist;
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std::vector<statistics::Scalar*> outTransLatHistRetries;
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//! Counter for the number of cycles when the transitions carried out
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//! were equal to the maximum allowed
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statistics::Scalar fullyBusyCycles;
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//! Histogram for profiling delay for the messages this controller
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//! cares for
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statistics::Histogram delayHistogram;
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std::vector<statistics::Histogram *> delayVCHistogram;
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} stats;
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};
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} // namespace ruby
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} // namespace gem5
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#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
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