1d64669473
The GPU device currently supports large BAR which means that the driver can write directly to GPU memory over the PCI bus without using SDMA or PM4 packets. The gem5 PCI interface only provides an atomic interface for BAR reads/writes, which means the values cannot go through timing mode Ruby caches. This causes bugs as the TCC cache is allowed to keep clean data between kernels for performance reasons. If there is a BAR write directly to memory bypassing the cache, the value in the cache is stale and must be invalidated. In this commit a TCC invalidate is generated for all writes over PCI that go directly to GPU memory. This will also invalidate TCP along the way if necessary. This currently relies on the driver synchonization which only allows BAR writes in between kernels. Therefore, the cache should only be in I or V state. To handle a race condition between invalidates and launching the next kernel, the invalidates return a response and the GPU command processor will wait for all TCC invalidates to be complete before launching the next kernel. This fixes issues with stale data in nanoGPT and possibly PENNANT. Change-Id: I8e1290f842122682c271e5508a48037055bfbcdf
101 lines
3.6 KiB
C++
101 lines
3.6 KiB
C++
/*
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* Copyright (c) 2013-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_SYSTEM_VIPERCOALESCER_HH__
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#define __MEM_RUBY_SYSTEM_VIPERCOALESCER_HH__
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#include <iostream>
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/ruby/protocol/PrefetchBit.hh"
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#include "mem/ruby/protocol/RubyAccessMode.hh"
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#include "mem/ruby/protocol/RubyRequestType.hh"
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#include "mem/ruby/system/GPUCoalescer.hh"
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#include "mem/ruby/system/RubyPort.hh"
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namespace gem5
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{
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struct VIPERCoalescerParams;
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namespace ruby
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{
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class DataBlock;
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class CacheMsg;
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struct MachineID;
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class CacheMemory;
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class VIPERCoalescer : public GPUCoalescer
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{
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public:
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typedef VIPERCoalescerParams Params;
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VIPERCoalescer(const Params &);
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~VIPERCoalescer();
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void writeCompleteCallback(Addr address, uint64_t instSeqNum);
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void invTCPCallback(Addr address);
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void invTCCCallback(Addr address);
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RequestStatus makeRequest(PacketPtr pkt) override;
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void issueRequest(CoalescedRequest* crequest) override;
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private:
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void invTCP();
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void invTCC(PacketPtr pkt);
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// make write-complete response packets from original write request packets
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void makeWriteCompletePkts(CoalescedRequest* crequest);
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// current cache invalidation packet
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// nullptr if there is no active cache invalidation request
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PacketPtr m_cache_inv_pkt;
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// number of remaining cache lines to be invalidated in TCP
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int m_num_pending_invs;
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// outstanding L2 invalidate packets
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std::unordered_map<Addr, std::vector<PacketPtr>> m_pending_invl2s;
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// a map of instruction sequence number and corresponding pending
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// write-complete response packets. Each write-complete response
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// corresponds to a pending store request that is waiting for
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// writeCompleteCallback. We may have multiple pending store requests per
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// wavefront at a time. Each time writeCompleteCallback is called, an entry
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// with a corresponding seqNum is popped off from map and returned to
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// compute unit.
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std::unordered_map<uint64_t, std::vector<PacketPtr>> m_writeCompletePktMap;
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};
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} // namespace ruby
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} // namespace gem5
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#endif //__MEM_RUBY_SYSTEM_VIPERCOALESCER_HH__
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