Steve Reinhardt 50a4ed87d0 Two fixes to try and get TLB miss cost more in line with real platform: ...

1) Add fault_handler_delay param to FullCPU to wait N cycles after
committing faulting instruction before fetching fault handler.
2) Make hw_rei a serializing instruction (flushes pipe, basically).

arch/alpha/isa_desc:
    Make hw_rei a serializing instruction (guarantees previous insts
    complete before hw_rei will issue).

--HG--
extra : convert_revision : 704cef65b3869be9eee724055cedb22114a78359

2005-03-01 22:32:14 -05:00

..

alpha

Two fixes to try and get TLB miss cost more in line with real platform:

2005-03-01 22:32:14 -05:00

isa_parser.py

Add support for CPU models to execute the effective

2005-02-03 20:47:11 -05:00