Nikos Nikoleris 7d70967aba arm: Add CMO support for Non-Cacheable memory ...

Cache Maintainance operations to the point of coherence are treated as
normal cahceable requests and clean and/or invalidate the caches of
all PEs.

Change-Id: Ia4a749c2318fe29c8601848b034b8315c4186c8a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5056
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

2017-12-05 11:47:01 +00:00

..

alpha

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

arm

arm: Add CMO support for Non-Cacheable memory

2017-12-05 11:47:01 +00:00

generic

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

hsail

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

mips

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

null

scons: Stop generating inc.d in the isa parser.

2017-10-17 18:57:50 +00:00

power

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

riscv

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

sparc

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

x86

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

isa_parser.py

alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.

2017-11-02 09:43:35 +00:00

micro_asm_test.py

Add a second section to make sure the ROM is extended properly.

2007-05-31 22:21:21 +00:00

micro_asm.py

scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access

2009-09-22 15:24:16 -07:00

SConscript

scons: Move Transform and termcap functionality into their own files.

2017-11-10 13:17:29 +00:00