Chander Sudanthi 7c479d7349 CP15 c15: enable execution with accesses to c15 registers ...

Previously, coprocessor accesses to CP15 c15 would fault.  This patch
enables accesses but prints out a warning, as the registers are not implemented.

2011-09-13 12:06:13 -05:00

..

arch

CP15 c15: enable execution with accesses to c15 registers

2011-09-13 12:06:13 -05:00

base

Stats: Add a sparse histogram stat object.

2011-08-19 15:08:05 -05:00

cpu

LSQ: Only trigger a memory violation with a load/load if the value changes.

2011-09-13 12:58:08 -04:00

dev

ARM: Add VExpress_E support with PCIe to gem5

2011-08-19 15:08:08 -05:00

doxygen

…

kern

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00

mem

Prefetch: Don't prefetch if address is in the write queue.

2011-09-13 12:06:13 -05:00

python

Stats: Add a sparse histogram stat object.

2011-08-19 15:08:05 -05:00

sim

LSQ: Only trigger a memory violation with a load/load if the value changes.

2011-09-13 12:58:08 -04:00

unittest

Stats: Add a sparse histogram stat object.

2011-08-19 15:08:05 -05:00

Doxyfile

…

SConscript

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00