Enable a gem5 system to be an SST::Component.
This change includes,
- SST::gem5Component: responsible for,
- initializing the Python environment for gem5
- instantiating gem5 SimObjects
- connecting SST::SSTResponderSubComponent to
gem5::OutgoingRequestBridge
- hanlding the gem5 event queue (no thread-synchronization)
- handling executing gem5 events
- SST::SSTResponderSubComponent: responsible for,
- receiving gem5 requests and sending the requests to
memory.
- sending responses to the corresponding
gem5::OutgoingRequestBridge.
- SST::SSTResponder: owned by SSTResponderSubComponent, the
actual actor that sends gem5's requests to memory.
- gem5::OutgoingRequestBridge: receives the requests from
gem5 and sends them to SST. This SimObject allows the initialization
requests to be cached and the receiver could query the
initialization data later on.
- gem5::SSTResponderInterface: the interface specifying how SST
communicates with gem5.
- A working example of a gem5/SST setup.
More information is available at ext/sst/README.md.
For installation instructions, please refer to ext/sst/INSTALL.md.
Change-Id: I6b81260ef825415bcfe72b8a078854f4c94de782
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50468
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
122 lines
4.5 KiB
C++
122 lines
4.5 KiB
C++
// Copyright (c) 2021 The Regents of the University of California
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef __TRANSLATOR_H__
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#define __TRANSLATOR_H__
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#include <sst/core/simulation.h>
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#include <sst/core/interfaces/stringEvent.h>
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#include <sst/core/interfaces/simpleMem.h>
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#include <sst/elements/memHierarchy/memEvent.h>
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#include <sst/elements/memHierarchy/memTypes.h>
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#include <sst/elements/memHierarchy/util.h>
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typedef std::unordered_map<SST::Interfaces::SimpleMem::Request::id_t,
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gem5::PacketPtr> TPacketMap;
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namespace Translator
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{
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inline SST::Interfaces::SimpleMem::Request*
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gem5RequestToSSTRequest(gem5::PacketPtr pkt,
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TPacketMap& sst_request_id_to_packet_map)
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{
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SST::Interfaces::SimpleMem::Request::Command cmd;
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switch ((gem5::MemCmd::Command)pkt->cmd.toInt()) {
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case gem5::MemCmd::HardPFReq:
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case gem5::MemCmd::SoftPFReq:
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case gem5::MemCmd::LoadLockedReq:
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case gem5::MemCmd::ReadExReq:
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case gem5::MemCmd::ReadReq:
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case gem5::MemCmd::SwapReq:
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cmd = SST::Interfaces::SimpleMem::Request::Command::Read;
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break;
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case gem5::MemCmd::StoreCondReq:
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case gem5::MemCmd::WriteReq:
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cmd = SST::Interfaces::SimpleMem::Request::Command::Write;
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break;
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default:
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assert(false && "Unable to convert gem5 packet");
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}
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SST::Interfaces::SimpleMem::Addr addr = pkt->getAddr();
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uint8_t* data_ptr = pkt->getPtr<uint8_t>();
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auto data_size = pkt->getSize();
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std::vector<uint8_t> data = std::vector<uint8_t>(
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data_ptr, data_ptr + data_size
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);
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SST::Interfaces::SimpleMem::Request* request = \
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new SST::Interfaces::SimpleMem::Request(
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cmd, addr, data_size, data
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);
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if ((gem5::MemCmd::Command)pkt->cmd.toInt() == gem5::MemCmd::LoadLockedReq
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|| (gem5::MemCmd::Command)pkt->cmd.toInt() == gem5::MemCmd::SwapReq
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|| pkt->req->isLockedRMW()) {
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request->setMemFlags(
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SST::Interfaces::SimpleMem::Request::Flags::F_LOCKED);
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} else if ((gem5::MemCmd::Command)pkt->cmd.toInt() == \
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gem5::MemCmd::StoreCondReq) {
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request->setMemFlags(
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SST::Interfaces::SimpleMem::Request::Flags::F_LLSC);
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}
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if (pkt->req->isUncacheable()) {
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request->setFlags(
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SST::Interfaces::SimpleMem::Request::Flags::F_NONCACHEABLE);
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}
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if (pkt->needsResponse())
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sst_request_id_to_packet_map[request->id] = pkt;
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return request;
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}
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inline void
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inplaceSSTRequestToGem5PacketPtr(gem5::PacketPtr pkt,
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SST::Interfaces::SimpleMem::Request* request)
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{
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pkt->makeResponse();
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// Resolve the success of Store Conditionals
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if (pkt->isLLSC() && pkt->isWrite()) {
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// SC interprets ExtraData == 1 as the store was successful
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pkt->req->setExtraData(1);
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}
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pkt->setData(request->data.data());
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// Clear out bus delay notifications
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pkt->headerDelay = pkt->payloadDelay = 0;
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}
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}; // namespace Translator
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#endif // __TRANSLATOR_H__
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